Hardware and Design Layout/Guidelines for P1010 DDR3 SRAM Interfaces

Document created by Omar Cruz Lopez Employee on Jul 24, 2012
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Routing the DDR Memory Channel

To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks

Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.

Routing DDR3 Data Signals

The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate.

An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the tDQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves:


Table 1: Byte Lane to Data Strobe and Data Mask Mapping

MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0
MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1
MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2
MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3
MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4
MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5
MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6
MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7
MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8

DDR Signal Group Layout Recommendations

Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation:

Table 2: DDR Signal Groups Layout Recommendations

Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock
When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group
Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together