bin Dong

MCF5482 SDRAM Controller Problem

Discussion created by bin Dong on Jun 4, 2010
Latest reply on Jun 10, 2010 by TomE

Recently I encounter a problem of ColdFire microprocessor MCF5482.

I find that when the VCC on the board of MCF5482 drops below 3.2V, the program will run away and the watchdog chip on the board will reset MCF5482.

The program is running in SDR SDRAM when it runs away, so I use a simple program that runs in Flash to test the writing and reading operation of SDRAM under the low-VCC (<3.2V) condition, then I find that the test program frequently halt during the reading operation. And when the program halts, the MCF5482 also does not response to GPT timer interrupt. Sometimes the test program halts for several minutes then continue running, sometimes increase the VCC to 3.3V also make the test program continue running.

I also find that the test program seldom halts if the SDRDQS drive capability is set to 24mA, currently the SDRDQS drive capability is set to 16mA, and other SDRAM controller related signals’ drive capability is set to 8mA. The SDRAM clock is 80MHz.

I have captured the waveforms during reading of SDRAM using Logic Analyzer and I don't find any violation of timing specification.

As below figure shows,

Figure-1 shows that test program runs about 1ms then halts during reading operation on SDRAM.

Figure-2 shows the waveform in details just before test program halts.


Below are my questions:

Does the waveform in above figure violate the timing specification of MCF5482 SDRAM controller timing specification?

What cause my test program halts during reading operation of SDRAM?

What status of MCF5482 is when it halts the test program and does not response to GPT timer interrupt?


Thanks a lot for kindly response!