LPSPI Receive Fifo Overrun in Master Mode with Stalling and TxMask Enabled

Discussion created by dciliske on May 1, 2020

Suffice to say, I'm fairly certain I've found an ugly new chip errata on the RT1060 (and presumably all other parts using the LPSPI module). When performing a continuing read, with CONT set in the original TCR, and CONTC set in the new TCR, and setting TXMSK in both, sometime after writing the new TCR, a RX fifo overrun may occur in Master Mode with NOSTALL clear.


This originally progressed from a workaround to the errata presented in RT1050 LPSPI last bit not completing in continuous mode.


I'm still working on gathering more specific data.