Just few question about LPC55S66 what are not clear from specifications.
1. Does it possible to identify reset reason of MCU ?
In K82 it was possible to identify what was reason of boot :
cold reset, sw reset, watchdog reset or external pin reset.
2. All FLEXCOMM interfaces mentioned to be supports USART and any USART can be configured like UART
without any problem ? I can see one bit in configuration but ...
3. In one page mentioned that programm flash has page size 256 bytes - other 512 bytes.
I think internal flash has minimal erasable unit as 512 bytes and with activated PRINCE module
I can erase/write flash memory on fly without any problem.
Erase/write time is quite long and what is MCU execution behaviour in this case ? It is stall ?
And I should wait end of operation in SRAM memory loop ?
How it can effect Core1 if Core0 update some flash pages ?
Should Core 1 is also execute code from SRAM if Core 0 erase/write program memory ?
What is also not so clear if Core0 and Core1 execute code from the same SRAM/Flash memory ?
Or SRAM banks should be different and flash memory resized some how ?
4. Basically any GPIO pin can be used for wakeup Core 0 from Power-down mode if
this pin is added to GINT0 or 1 group.
5. What exact means WAKEUP_FLEXCOMM3 support ?
For example SPI wakeup due clock eghe on SCK line and etc.
But wakeup of MCU from Power-down mode take > 300 us and some SPI data might be lost already.
Or how so long wakeup time is handled by FLEXCOMM controller ?
6. Is any limitation for some peripherals/memory how the can be resized between Core0 and Core1 ?
Or just access right like secure/NS/Priv/nonPri is define accesses ?
Thank you !