Dear,
I want to config u-boot 2018.3_4.14.98 with LAN8720 for iMX6DL.
I modified the source for that.
However, It does not detect LAN8720.
boot log is shown below:
U-Boot 2018.03-imx_v2018.03_4.14.98_2.0.0_ga+g87a19df (May 17 2019 - 17:21:02 +0900)
CPU: Freescale i.MX6DL rev1.3 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 52C
Reset cause: POR
Model: Freescale i.MX6 DualLite SabreSD CMOS Board
Board: MX6-SabreSD
DRAM: 256 MiB
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc2(part 0) is current device
flash target is MMC:2
Net: No ethernet found.
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot: 0
=>
but, when I changed value of env. value, ethaddr to 00:01:02:03:04:05
It detect LAN8720 as following :
mmc2(part 0) is current device
flash target is MMC:2
Net: eth0: ethernet@02188000 [PRIME]
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot: 0
=>
Why is this happening?
I need your help.
in arch\arm\dts\imx6qdl-sabresd.dtsi
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
in include\configs\mx6sabre_common.h
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#ifdef CONFIG_DM_ETH
#define CONFIG_ETHPRIME "eth0"
#else
#define CONFIG_ETHPRIME "FEC"
#endif
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
in board\freescale\mx6sabresd\mx6sabresd.c
static void setup_fec(void)
{
imx_iomux_set_gpr_register(1, 21, 1, 1);
enable_fec_anatop_clock(0, ENET_50MHZ);
fec_phy_reset();
}
