So this is a three-pronged question...
- How does one generate the C-format DCD header components such as "evkbimxrt1050_sdram_ini_dcd.c"?
- Where can I find the MCU Config Tools file (.MEX) which generated the clock settings found in "evkbimxrt1050_sdram_ini_dcd.c"?
- Is there an RT1050 SDRAM config tool specifically for generating SDRAM settings which then get plugged into the DCD data?
Part 1... In nearly every example project for the RT1050 EVKB, there is a subdirectory named "xip". And in that directory there are three sets of source/header files, "evkbimxrt1050_sdram_ini_dcd", "evkbimxrt1050_flexspi_nor_config", and "fsl_flexspi_nor_boot". Each of these files contains XIP boot header information, specifically for initializing SDRAM, describing the FlexSPI/HyperFlash device capabilities, and describing the boot image, respectively.
How was "evkbimxrt1050_sdram_ini_dcd.c" and the other source files generated? At least, I'm assuming they were all generated, not written by hand; at a minimum, the SDRAM init settings surely had to be machine-generated. I've found documents like this one, but that only describes doing post-processing on S19 and binary images and such, not generating source code like that in the "xip" directory. These files don't appear to be generated by the MCU Config Tools. Which utility created them?
Part 2... I'm creating my own RT1050 project, and I'm approaching the daunting task of setting all of the clock generation options. I'd like to set up my MEX file to have the same clock settings that went into the XIP SDRAM settings. But it seems like all of the clock_config settings in the SDK examples are set to defaults as well. I added some code to my project to extract what the clocks are once the system has been initialized (I have SKIP_SYSCLK_INIT defined so that my code doesn't overwrite what the boot ROM set up). Here's my output:
600000000 Hz kCLOCK_CpuClk
600000000 Hz kCLOCK_AhbClk
163862064 Hz kCLOCK_SemcClk
150000000 Hz kCLOCK_IpgClk
75000000 Hz kCLOCK_PerClk
24000000 Hz kCLOCK_OscClk
32768 Hz kCLOCK_RtcClk
1200000000 Hz kCLOCK_ArmPllClk
480000000 Hz kCLOCK_Usb1PllClk
261818172 Hz kCLOCK_Usb1PllPfd0Clk
246857130 Hz kCLOCK_Usb1PllPfd1Clk
332307684 Hz kCLOCK_Usb1PllPfd2Clk
576000000 Hz kCLOCK_Usb1PllPfd3Clk
24000000 Hz kCLOCK_Usb2PllClk
528000000 Hz kCLOCK_SysPllClk
0 Hz kCLOCK_SysPllPfd0Clk
0 Hz kCLOCK_SysPllPfd1Clk
327724128 Hz kCLOCK_SysPllPfd2Clk
0 Hz kCLOCK_SysPllPfd3Clk
24000000 Hz kCLOCK_EnetPll0Clk
24000000 Hz kCLOCK_EnetPll1Clk
24000000 Hz kCLOCK_AudioPllClk
24000000 Hz kCLOCK_VideoPllClk
So it looks like the XIP DCD settings set up the system PLL (PLL2) PFD2 output to 327 MHz, making the SEMC clock 163 MHZ (closest to 166 MHz, presumably), and also set the USB1 PLL (PLL3) PFD0 output to 261 MHz for FlexSPI operation. Everything else is at defaults. Are PLL2_PFD2 and PLL3_PFD0 the only clock settings that matter when setting up FlexSPI and SDRAM?
Part 3... Is there some special utility NXP used to generate all of the SDRAM timing data that's presumably encoded in the DCD data? If one just plugs in the numbers from the SDRAM datasheet, the SDRAM should just work, right?
I realize this is a lot, but I'm really trying to get to the bottom of what was used to generate the DCD data used in all of the examples, so I can make sure my custom project is set up correctly. Thanks.