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S32K LPSPI don't receive message

Question asked by lei liu on Feb 14, 2019

I want to communicate via SPI and W25q64, but I can't receive data.

lpspi_tx_cmd_config_t Spi_TxCmdCfgSet = {
.whichPcs = LPSPI_PCS1, /* PCS=1: Transfer using PCS1 */
.width = LPSPI_SINGLE_BIT_XFER, /* WIDTH=0: Single bit transfer */
.clkPhase = LPSPI_CLOCK_PHASE_2ND_EDGE, /* CPHA=0: Change data on SCK lead'g, capture on trail'g edge*/
.clkPolarity = LPSPI_SCK_ACTIVE_LOW, /* CPOL=0: SCK inactive state is HIGH */
.lsbFirst = false, /* LSBF=0: Data is transfered MSB first */
.txMask = false, /* TXMSK=0: Normal transfer: data loaded from tx FIFO */
.rxMask = false, /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
.contTransfer = false, /* CONT, CONTC=0: Continuous transfer disabled */
.contCmd = false, /* Master option to change cmd word within cont transfer. */
.frameSize = 8 , /* FRAMESZ=7: # bits in frame = 7+1=8 */
.preDiv = 1, /* PRESCALE=2: Functional clock divided by 2*2 = 4 */
.byteSwap = false, /* BYSW=0: Byte swap disabled */
};
void OL_SDK_LPSPI_Init(void)
{
PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B2: MUX = ALT3, LPSPI1_SCK */
PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B3: MUX = ALT3, LPSPI1_SIN */
PORTB->PCR[4]|=PORT_PCR_MUX(3); /* Port B4: MUX = ALT3, LPSPI1_SOUT */
PORTB->PCR[5]|=PORT_PCR_MUX(3); /* Port B5: MUX = ALT3, LPSPI1_PCS1 */


PCC->PCCn[PCC_LPSPI0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK
| PCC_PCCn_PCS(6) /* Enable PCS (40 MHz func'l clock) */
| PCC_PCCn_CGC_MASK; /* Enable clock for LPSPI regs */


LPSPI_Disable(LPSPI0); /* Disable module for configuration */
LPSPI_SetIntMode(LPSPI0,LPSPI_ALL_STATUS,false); /* Interrupts not used */
LPSPI_SetTxDmaCmd(LPSPI0,false); /* DMA not used */
LPSPI_SetRxDmaCmd(LPSPI0,false); /* DMA not used */
LPSPI_SetMasterSlaveMode(LPSPI0, LPSPI_MASTER); /* Set for master mode */
LPSPI_SetPinConfigMode(LPSPI0, LPSPI_SDI_IN_SDO_OUT, LPSPI_DATA_OUT_RETAINED, true);
LPSPI_ClearStatusFlag(LPSPI0,LPSPI_ALL_STATUS);

LPSPI_SetBaudRateDivisor(LPSPI0,2); /* SCKDIV=8: SCK divider =2+2 = 4 (1 usec: 500000 baud rate) */
LPSPI_SetDelay(LPSPI0, LPSPI_SCK_TO_PCS, 4); /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
LPSPI_SetDelay(LPSPI0, LPSPI_PCS_TO_SCK,9); /* PCSSCK=9: PCS to SCK delay = 9+1 = 10 (1 usec) */
LPSPI_SetDelay(LPSPI0, LPSPI_BETWEEN_TRANSFER, 8);/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
LPSPI_SetPcsPolarityMode(LPSPI0,LPSPI_PCS1 ,LPSPI_ACTIVE_LOW);
LPSPI_SetSamplingPoint(LPSPI0, false);

LPSPI_SetRxWatermarks(LPSPI0,0); /* RXWATER=0: Rx flags set when Rx FIFO >0 */
LPSPI_SetTxWatermarks(LPSPI0,3); /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI_SetTxCommandReg(LPSPI0,&Spi_TxCmdCfgSet);


LPSPI_Enable(LPSPI0); /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
}

uint8_t OLA_SDK_LPSPI_WirteRead(LPSPI_Type * base,uint8_t Send_Value)
{
uint8_t DataValue = 0;

 

while((base->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
base->TDR = Send_Value; /* Transmit data */
base->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

 

while((base->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
DataValue= base->RDR; /* Read received data */
base->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
return DataValue;
}

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