Hi santhosh,
The method you are describing is correct! (It is really quite simple).
If you have a lot of bytes to send then the TDRE (not TDRF) bit is only clear for an instant as you make it full again in the interrupt.
Also if the SCI is not setup properly (TE set) the bytes won't shift out and you will end up with it not setting.
Normal code for this never actually checks for the flag to be clear anyway.
If using polling you check for it to be set and write to SCID.
If using interrupts there is no need to test it at all. Being set triggers the interrupt automatically and in the interrupt you simply read SCISC and write to SCID.
I think we will need to see your code to take this further.
P.S. Remember that this bit is an indicator for the buffer and not the shift register. Under certain conditions the byte will fall straight through the buffer into the shift register and so even though you write to SCID the TDRE will not necessarily clear.
Message Edited by peg on
2008-11-14 08:55 AM