AnsweredAssumed Answered

RGMII_RX_CTL cannot output high level signal when configured as GPIO

Question asked by Shawn Xiao on May 16, 2018
Latest reply on May 17, 2018 by igorpadykov

Hi FSL engineer,

I want the pins RGMII_RX_CTL and RGMII_RD3 work as GPIO(output only). And the other signals for these pins were commented. Finally the pin cannot out '1' signal and always keep low. But I replace the pins with GPIO_7 and GPIO_8. It works normally. 

I checked the RM and cannot find the difference between these two pairs of pins when configured as GPIO. Could you please advise me how to fix this issue? Thank you.



SoC:i.MX 6QP, OS: M6.0


MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24  0x00013030 
MX6QDL_PAD_RGMII_RD3__GPIO6_IO29     0x0001B030


usb2553-enctlgpio = <&gpio6 24 0>;
usbfault-enctlgpio= <&gpio6 29 0>;