RGMII_RX_CTL cannot output high level signal when configured as GPIO

[hi_shawn]

Hi FSL engineer,

I want the pins RGMII_RX_CTL and RGMII_RD3 work as GPIO(output only). And the other signals for these pins were commented. Finally the pin cannot out '1' signal and always keep low. But I replace the pins with GPIO_7 and GPIO_8. It works normally. 

I checked the RM and cannot find the difference between these two pairs of pins when configured as GPIO. Could you please advise me how to fix this issue? Thank you.

/***********************************************************/ 

SoC:i.MX 6QP, OS: M6.0

MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24  0x00013030 
MX6QDL_PAD_RGMII_RD3__GPIO6_IO29     0x0001B030

==========

usb2553-enctlgpio = <&gpio6 24 0>;
usbfault-enctlgpio= <&gpio6 29 0>;

/**********************************************************/

[hi_shawn]

Hi Igor,

Pins RGMII_RX_CTL and RGMII_RD3 don't connect to 8031.  I want configure them to ALT5 and ALT5. Please refer to the pictures below. As i mentioned, the pins GPIO_7 and GPIO_8 are OK. But i cannot find the root cause. Anything else i should care about?

[igorpadykov]

Hi Shawn

please attach jtag debugger and try to set outputs of these pads using jtag.

Best regards
igor

[igorpadykov]

Hi Shawn

is there some rgmii circuit on the board, as for example on i.MX6QP Sabre SD schematic SPF-28857
these two signals are connected to outputs of AR8031 (U516) RGMII_RXD3, RGMII_RXDV.
In general one can attach jtag and check iomux settings and try manually set them to '1' signal.

Best regards
igor
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