AnsweredAssumed Answered

DDR3 Clock Termination!

Question asked by Qammar Abbas on Apr 19, 2018
Latest reply on Apr 19, 2018 by Bulat Karymov


I am trying to interface T1042 with DDR3 memory chips in fly by toopology. The DDR3 designer checklist (AN3940) suggests that the differential clock pairs should have a differential termination on the memory side. Why is that necessary?
Moreover, my simulation results on Hyperlynx show better clock waveform when there is no differential termination. I have just used the VTT termination.