I am trying to configure the DDR Memory Controller's registers of ls1043a.I am unable to comprehend the "DQ mapping registers." Can anybody explain what they are for and how to configure them for support ecc.
Please refer to the JEDEC Standard No. 21-C
Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules:
“Bytes 60~77 (0x03C~0x04D): Connector to SDRAM Bit Mapping
These bytes document the connection between data signals at the edge connector of a module to the DDR4 SDRAM inputs pins for package rank 0 of the module. This information is used by the controller to route data onto the correct bit lines for CRC transmission as described in the DDR4 SDRAM data sheet JESD79-4. Each byte describes the mapping for one nibble (four bits) of data. In addition, each SPD byte describes the mapping between package rank 0 bits and equivalent bits in other ranks.”
The CRC generation and checking is described in the JEDEC Standard No. 79-4, 4.16 CRC
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