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MMPF0100 F0 and iMX6 Power Sequencing

Question asked by markwilliams on Feb 28, 2018
Latest reply on Mar 1, 2018 by Jose Alberto Reyes Morales

Hi,


I am looking to use an MMPF0100 PMIC with F0 configuration for an iMX6 design. As I understand it the typical connections would be:

 

VDD_ARM_IN from SW1A/B

VDD_SOC_IN from SW1C

 

The F0 configuration enables SW1A/B 2ms prior to VDD_SOC_IN.

 

I am looking to use the internal POR so I see in the datasheet that: "VDD_SOC_IN can be supplied before VDD_ARM_IN with a max delay of 1ms".

 

With F0 configuration VDD_ARM_IN is supplied first (2ms before VDD_SOC_IN). Can I just verify that there are no time constraints supplying power in this order? The datasheet just mentions the 1ms when supplied the other way round.

 

Another post seemed to suggest that this still violated the datasheet but I cannot see why.

 

Thanks, Mark

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