I am reading the URM for the processor, the HSADC. I find some settings difficult to understand.
The 41.3.5 HSADC Channel List Register 1 (HSADCx_CLIST1) and the other CLISTn: if the sequential scan is planned I see a sense in having a totally random use of the two ADCA/B so each sample can refer to ANAn or ANBn, but in parallel mode there is no way to write on SAMPLE0 the value: 1000 Single Ended: ANB0. The rule I extract seems to be: the first SAMPLE0 to SAMPLE7 refer mandatory to the ADCA while the others to the ADCB. This seems to be parallel coerent with HSADCx_SDIS register where the 0 to 7 bits refer to ADCA and the other to ADCB.
Is it correct???
Another question is on page 1024 of the URM Figure 41-3. HSADC Parallel Scan Mode. It is not clear what means SAMPLEn is from ADLST1 or ADLST2. SAMPLEm is from ADLST3 or ADLST4. What are the ADLSTn?
I searched for the string ADLST in chapter 41 no match is found....
The other open question is how to map the input pins to the ANAn ANBn input in all of the figures. The pinout of the processors shows something like HSADC1A _CH11. This is referring to the ANA11 of the the ADCA of the HSADC1, which is selected with the ANA7 logical input in turn through the CH7_SELA[2:0] bits set to 2.
A similar way map the pinout of the processor to the input slots.
Is it correct??