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ENET Clocking Problem[MCP5748G]

Question asked by Hedi BASLY on Feb 16, 2018
Latest reply on Feb 20, 2018 by Hedi BASLY

Hello,

 

I'm working with MPC5748G, i first start my project on Eval Board from NXP which have a 40MHz external oscillator, after that when the code arrived to a mature state, we changed the project to it's real target board, which is custom board with external oscillator at 16MHz,

 

 

when the code is downloaded to the target board with 16MHz oscillator. no PLL configuration is done but some communication modules kept working fine which are CAN, I2C and Ethernet.

 

I analysed the situation and i figured out that for the CAN and the I2C there is really no problem about the clock wrong frequencies but for the ETHERNET i think that we should have a problem. but we don't !!

 

So her is my question, with 16MHz external oscillator and the same PLL config from the eval board that give 160 from 40. PLLDV[MFD] = 16, PLLFD[MFN] = 0, PLLDV[PREDIV] = 1 }==> 40 *(16/4) = 160MHz.

but with 16MHz } 16 *(16/4) = 64MHz 

==> so my system is runnig at 64MHz

in reference manual Paragraph 9.7.2 according to clock restriction my configuration does not respect the ENET AHB restrictions nor the ENET timer clock period which connected to F40 = 16MHz due to wrong config ==> period 62.5ns

 

The problem is that the ENET module works fine in both cases and i can't find why.

Any explanation would be appreciated. just ask me me if you need more information.

MC_CGM_AC2_SC is not reconfigured in my code so ENET is clocked from F40.

for exemple when system clock is 160MHz the F40 is 1/4 which is 40Mhz, when we have 64Mhz does the ration 1/4 for F40 keep having sens to give F40 = 16Mhz ? 

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