AnsweredAssumed Answered

LS1043A-RDB: LSDK 17.12: DDR4 timing: clocks vs nanoseconds

Question asked by Cyril Strejc on Feb 13, 2018
Latest reply on Feb 13, 2018 by ufedor

I'm inspecting the LSDK 17.12 with the QorIQ LS1043A reference design board (LS1043A-RDB).

 

I'm confused by some of DDR4 timing settings:

 

In U-Boot, let's consider CONFIG_SYS_DDR_RAW_TIMING defined, the DDR4 timing is NOT read from the EEPROM, but it's hard-coded into the U-Boot's source code:

 

u-boot/board/freescale/ls1043ardb/ddr.c:

/* DDR model number: MT40A512M8HX-093E */
#ifdef CONFIG_SYS_DDR_RAW_TIMING
dimm_params_t ddr_raw_timing = {
     .n_ranks = 1,
     .rank_density = 2147483648u,
     .capacity = 2147483648u,
     .primary_sdram_width = 32,
     .ec_sdram_width = 0,
     .registered_dimm = 0,
     .mirrored_dimm = 0,
     .n_row_addr = 15,
     .n_col_addr = 10,
     .bank_addr_bits = 0,
     .bank_group_bits = 2,
     .edc_config = 0,
     .burst_lengths_bitmask = 0x0c,

     .tckmin_x_ps = 938,
     .tckmax_ps = 1500,
     .caslat_x = 0x000DFA00,
     .taa_ps = 13500,
     .trcd_ps = 13500,
     .trp_ps = 13500,
     .tras_ps = 33000,
     .trc_ps = 46500,
     .trfc1_ps = 260000,
     .trfc2_ps = 160000,
     .trfc4_ps = 110000,
     .tfaw_ps = 21000,
     .trrds_ps = 3700,
     .trrdl_ps = 5300,
     .tccdl_ps = 5355,
     .refresh_rate_ps = 7800000,

Let's focus for example to T_FAW. According to the Micron's datasheet, the minimum T_FAW for MT40A512M8-093E (DDR4-2133) should be "greater of 20CK of 21ns" (Table 157 of the datasheet). The MT40A512M8 page size is 1KB (Table 2 in the same datasheet).

Micron DDR4 T_FAW timing

The tfaw_ps parameter of the structure is set correctly to 21ns (.tfaw_ps = 21000), but this leads to the TIMING_CFG_2 register of the LS1043A DDR registers is set to 0x0048C111, which means the FOUR_ACT in the register is set to 0x11 which means 17 cycles. I have read the TIMING_CFG_2 register value from U-Boot's prompt:

 

U-Boot 2017.07 (Jan 11 2018 - 10:01:08 +0100)

SoC: unknown (0x87920410)
Clock Configuration:
CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz
CPU3(A53):1600 MHz
Bus: 400 MHz DDR: 1600 MT/s FMAN: 500 MHz
Reset Configuration Word (RCW):
00000000: 08100010 0a000000 00000000 00000000
00000010: 14550002 80004012 60040000 c1002000
00000020: 00000000 00000000 00000000 00038800
00000030: 00000000 00001100 00000096 00000001
...
Hit any key to stop autoboot: 0
=> md.l 108010C 1
0108010c: 11c14800

The number of cycles (17) respects 21ns minimum T_FAW time according to the datasheet, because 800MHz DDR clock means clock time 1.25ns and 17*1.25ns = 21.25ns, but it seems to me it does not respect statement in the datasheet, that minimum T_FAW should be "greater of 20CK or 21ns", the FOUR_ACT should be set to 20 cycles according to my understanding.

 

So, please, where is my understanding wrong? How it's possible the LSDK is happy with FOUR_ACT set to 17 cycles? 

Outcomes