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Question on SRAM size / availability

Question asked by Praveen Hegde on Jan 29, 2018
Latest reply on Jan 29, 2018 by Mark Butcher

Hi.

 

I am using K65 MCU for my application. This has 256 KBytes of RAM (    SRAM_UPPER : 192 KB and SRAM_LOWER : 64 KB) and the access rule is as defined below.

 

4.12 SRAM accesses
The SRAM is split into two logical arrays that are 32-bits wide.
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
port.
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the

backdoor port.

 

My question is, can my application use both these portions of the SRAM seamlessly? In other words, both the sections are available for application to use (total 256 KB) ? Are there any constraints for the use?

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