Laurent Cremmer

[MCF54450] Enabling D-Cache && I-Cache 'crashes' the processor

Discussion created by Laurent Cremmer on Oct 3, 2008
Latest reply on Oct 7, 2011 by Brian Ramey
Hi Everyone,

I've been trying to get the D&I cache working on a custom board we made, and all I get is the processor 'crashing' !

The custom board is mainly designed after the MCF54455EVB demonstration board, uses the same DDR2 chips, only difference is we have a slightly bigger flash boot chip and we run it of a 24Mhz xtal, not a 33Mhz one.

The board runs fine (from boot flash, from ddr, from static ram) until I try to enable the processor cache (CACR is configured to enable caching but disabling I & D cache by default. ACRx are then used to enable caching of the bootrom and the ddr).

As soon as I do that, the processor either stops, or crashes or even resets itself. I tried to enable to data cache only, to cache the bootrom or the ddr only, it just crashes. If I am in the middle of transmitting to the UART, the UART output goes wild and just transmits random piece of garbage.

It even does that If the code is running in the internal static ram which is cache-inhibited anyway !!!

If I am running the EXACT SAME CODE (but for the PLL configuration) on the demonstration board it runs just fine.

I've trippled check the DDR2 and FlexBus timings against the chips' datasheets, nothing wrong here.

The code I am running does nothing more than transmitting to the UART and performing a memory test on the DDR (walking ones and son on).  it is small enough to fit in the static ram.

Is there any difference between the 54455 & 54450 die that could cause that ? could it be an external hardware issue ?

Any hint would be greatly appreciated, I'm feeling a bit stuck now.

Regards,
Laurent.

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