Mauro Salvini

iMX6SX M4 FreeRTOS BSP: EPIT example wrong

Discussion created by Mauro Salvini on Nov 9, 2017
Latest reply on Nov 13, 2017 by Carlos_Musich


using example code for EPIT configuration contained in FreeRTOS BSP 1.0.1 for iMX6SX, a colleague found an error on counter load value set into EPIT.

This is a code excerpt from examples/imx6sx_sdb_m4/driver_examples/epit/main.c:


    /* Divide EPITA clock source frequency by 2 inside EPIT module */
    /* Divide EPITB clock source frequency by 2 inside EPIT module */


    /* Get EPITA clock frequency */
    freqA = get_epit_clock_freq(BOARD_EPITA_BASEADDR)/2;
    /* Get EPITB clock frequency, 32768Hz */
    freqB = 32768/2;


    /* Set both EPIT modules to 1 second duration */
    EPIT_SetCounterLoadValue(BOARD_EPITA_BASEADDR, freqA);
    EPIT_SetCounterLoadValue(BOARD_EPITB_BASEADDR, freqB);
    /* The first interrupt occured at 0.5 second */
    EPIT_SetOutputCompareValue(BOARD_EPITA_BASEADDR, freqA/2);
    EPIT_SetOutputCompareValue(BOARD_EPITB_BASEADDR, freqB/2);


Internal EPIT prescaler is set to use source clock divided by two, so freqA and freqB are calculated as original frequency divided by two. Load value is set to frequency (so if EPITA source clock is 24MHz, half frequency is 12MHz, load value is 12000000), and there is the error: with this value, counter fires an interrupt after 12000001 clocks, because it decrements from 12000000 to 0. With a source frequency of 24MHz/2 = 12MHz, it is a 83.333 ns error. For large interrupt periods it is less visible, but with narrow periods it is a significant error.