Our project is VCU design, and we use MPC5744P as CPU. When designing the drivers of ADCs, we found it's hard to control the sample rate.
In the MPC5744P's reference manual, it is said that ADC's highest sample rate is 1M at 80MHz. But there's no detailed description about how to config the registers to set sample rate to the value exactly what we wanted.
We found some description about conversion time in the 36.5.11 of reference manual, which says the total conversion time is decided by the value of ADC_MCR[ADCLKSEL], CALBISTREG[OPMODE], CTRx[INPSAMP]. But it's confusion about the relationship between the conversion time and simple rate.
As the reference manual says, the smallest value of CTRx[INPSAMP] is 8, that is to say, when CTRx[INPSAMP]=8d, the sample rate of ADC should be 1M. But if the configuration is ADC_MCR[ADCLKSEL]=1, CALBISTREG[OPMODE]=001b, CTRx[INPSAMP]=8d, the single conversion time should be 2+8+((12+1)*4)+2=64 cycles of AD_clk, and the continuous conversion time shoude be 8+((12+1)*4)+2=62 cycles of AD_clk. So in the configuration above, the sample rate in single conversion mode and continuous conversion mode are 80/66M and 80/62M, which are larger than the highest sample rate announced.
If the relationship between the conversion time and simple rate is not Simple Rate= Frequency of ADC_CLK/Conversion time, what is the true relationship?
We did some experiments, set ADC_MCR[ADCLKSEL]=1, CALBISTREG[OPMODE]=001b, CTRx[INPSAMP]=8d, and used a signal generator to generate a 1KHz triangular wave to the ADC channel, and let the MPC5744P sampled 1000 samples from the signal, then used MATLLAB simulated the waveform, but found there were about 6 periods of triangular wave, so the sample rate calculated is 80MHz/(6*1000)=133KHz. That don't make sense.
So the question is: how to set the ADC sample rate as we wanted?
Looking forward for your response!
Thanks a lot!