AnsweredAssumed Answered

LS1012A no Eth PHY, chip-to-chip connection

Question asked by Jan Modaal on Oct 13, 2017
Latest reply on Sep 28, 2018 by Markus Niebel

Hello,

 

I have a PHY-less design with LS1012A.

 

SGMII interface is connected chip-to-chip to a managed Gbit switch. The switch is controlled using SPI commands.

The MDIO pins of LS1012A are dangling. The Gbit switch has no MDIO bus.

 

How to force PPFE to assume link is Up, 1Gbit full Duplex, both in U-Boot and Linux kernel ?

 

I found a vague note in QorIQ-SDK-2.0-1703-IC-Rev0.pdf, p.69 Table 13, Open issue:
QLINUX-6082: "Macless devices are not supported (neither in the Linux kernel nor in usdpaa) on LS1043A and LS1046A"

Is LS1012A also affected ?

 

Regards,

Jan

Outcomes