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Question asked by Steve Retzlaff on Sep 11, 2017
Latest reply on Sep 12, 2017 by igorpadykov

Hi, we are trying to maximum performance using an I.MX6 SoloX chip as the PCIe master/RC when reading 32-bit integer data from a gen1 EP based on a directly connected on-board FPGA. Currently we are able to get only 500 K 32-bit words/second from the FPGA FIFO (implemented on BAR0) when reading from software on the ARM, in the Linux kernel. 


Because this is a slotless direct connection from the I.MX6 RC to the FPGA EP, there is no opportunity to monitor with a PCIe Analyzer. We can, however, monitor PCIe activity with ChipScope from the FPGA.


Based on measuring the data received on the ARM and the timing of the read requests on the PCIe interface, we are reasonably certain the EP is sending one word (32 bits) per TLP instead of the maximum of 16 (64 bytes).  We can’t seem to get read bursting to work using either ioread32() or memcpy() calls from the I.MX6.


Can you tell us how to obtain maximum performance for reads from a PCIe EP using the i.MX6 RC?