HQ Liu

MCP5775 SDPLL can't lock when using external clock source

Discussion created by HQ Liu on Aug 3, 2017


I'm using a 3.3v LVCMOS external clock source to drive MPC5775 now. The PLL0 can lock normally, but SDPLL can't lock. The code will always pending on while(AFE.PLLSTS.B.LOCK == 0); 

The PLLSTS register show 0 on bit0, bit1, bit2 and bit15.

The code can lock correctly on the same board with a crystal. The only difference on code is  AFE.OSCCTRL.B.EN_EXT setting.

Would you please let me know that if I missed something to set?