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MPC5777M : interrupt hardware mode configuration

Question asked by Paulo DA SILVA PINTO on Jul 13, 2017
Latest reply on Jul 20, 2017 by Paulo DA SILVA PINTO


Until now, I've set up the INTC controller in software mode keeping the HVENx bits to 0.

At the same time, the IVPR register was pointing to an exception vector table (from critical exception vector to floating point round vector).

With this mode, I was able to get an external interrupt exception vector where I can identify the source of the interrupt (looking at the IACKR register of the INTC and acknoledge it with the EOIR register).. 


Now I'm trying to use the hardware mode (putting the necessary HVENx bits to 1). I've got a ISR table aligned to 256bytes and where each entry has a size of 4 bytes and I set the IVPR to the address of this table.

How do I inform the core to find the exceptions vector. With the 5566, we have used the mtivor instruction to set each ivor individually but how do we perform analog operation in the MPC5777M ?

Do you have please any piece of code and linker command file where can I found an implementation of the hardware mode ?


Best regards