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power on configuration values latching problem in mpc885

Question asked by padmayarraguntla on Jun 13, 2017
Latest reply on Jun 15, 2017 by padmayarraguntla

At power on ebdf  and others are not updating . clk out is 18.75MHz instead of 37.5MHz. Modck is 11 at power on reset. If we see in debug mode PLPRCR ( EBDF) is 00 only instead of 01. Data bus(0:15) transitions are  as per configuration set values  with respect to Hard reset, but not latching into the processor. PLL is locking to 18.75MHz/75mhz. Please clarify. Once in a while it is locking to 37.5mhz and immediately  to 18.75mhz.