To whom it may concern,
Thank you for your attention to this letter. I have some questions about MPC 8270 and need your help.
On the mpc8270, we designed a multi-task application. It consists of the following tasks:
-Task A: it works periodically, issues a PCI read request, and sends a heartbeat to task B. In a failed state, the PCI device is turned off, so task A triggers the machine check exception (0x200) because the TEA signal, and cannot send the heartbeat.
-Task B: it receives heartbeat, and deletes and rebuild task A when reception is unsuccessful.
-Interrupt: the system has 250ms timer interrupter, which occurs periodically and triggers the external interrupter exception (0x500).
Since the 0x200 exception is an asynchronous exception, it will occur within several instructions after the PCI read request instruction. In the fault scene, we detected that a very short time (less than 200ns) after the 0x500 exception trigger, and the machine detection exception was also triggered. We observed that the CPU responds with the 0x200 exception and performs exception handling. In the exception handling, register SRR0 value is one of the instruction addresses of the task A, not the address of external interrupter exception. But the register SRR1 is an error value (0x1000) and is not the MSR state in the running of task A(the correct value should be 0xB932). Due to the wrong SRR1 value, the system crashes in subsequent execution.
Since 0x200 has a higher priority than 0x500, we suspect that hardware logic has encountered an anomaly error during 0x200 preemption of 0x500 exception. This error causes SRR1 to store the state of 0x500, but not the correct program status.
We would like to know whether the hardware has the fault we have guessed, and how the software should do to avoid the problem in the current situation.
Look forward to your feedbacks and suggestions soon.
Very truly yours.