AnsweredAssumed Answered

Erroneous MDIO register documentation or definitions for mEMAC?

Question asked by Martin Etnestad on May 18, 2017
Latest reply on May 21, 2017 by Martin Etnestad

Hi all,

I have come across something extremely confusing with the #defines at the end of fsl_memac.h, available in FreeScale's U-Boot Git repository here: http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/tree/include/fsl_memac.h

 

If you compare the defines with the register definitions in f.ex. "QorIQ LS1046A Data Path Acceleration Architecture (DPAA) Reference Manual", section "6.4.3.4 MDIO Ethernet Management Interface Registers", almost all of them appear to be "backwards".
Allow me to use MDIO_STAT as an example:

#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) /* Wrong! Should be 16 */
#define MDIO_STAT_BSY (1 << 0) /* Correct! */
#define MDIO_STAT_RD_ER (1 << 1) /* Wrong! Should be 30 */
#define MDIO_STAT_PRE (1 << 5) /* Wrong! Should be 26 */
#define MDIO_STAT_ENC (1 << 6) /* Wrong! Should be 25 */
#define MDIO_STAT_HOLD_15_CLK (7 << 2) /* Wrong! Should be 27 */
#define MDIO_STAT_NEG (1 << 23) /* Wrong! Should be 8 */

The only bit definition that appears correct according to documentation is MDIO_STAT_BSY.
All the other definitions are backwards, i.e., singular bit N is "moved" to 31-N.

 

There is also a #define for MDIO_DATA_BSY, which I can't find any mention of in the MDIO_DATA register definition.
Does this bit exist at all?

 

What's going on here? Is the documentation for the MDIO registers wrong?

Or am I misunderstanding something?

 

Best regards,
    Martin Etnestad

Outcomes