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LPUART receive interrupts supported?

Question asked by Frederick Soo on May 16, 2017
Latest reply on May 19, 2017 by Frederick Soo

The Reference Manual 47.4.6 says that the transmitter has two interrupts - but does not mention any receiver interrupts.  The register description for CTRL[RIE] indicates that the receive interrupt is triggered on receive buffer full. Are interrupts on receive buffer full supported?  Or is it intended to use DMA and receive interrupt that way?  

 

I've set the NVIC ISR vector for LPUART1 receive interrupts:

 

 

S32_NVIC->ICPR[1] = 1 << (33 % 32); /* clr any pending IRQ*/

S32_NVIC->ISER[1] = 1 << (33 % 32); /* enable IRQ */

S32_NVIC->IP[8] =0x0A; /* priority 10 */

 

and enabled CTRL[RIE]:

 

LPUART1->CTRL=0x002C0000;    /* Enable transmitter & receiver, no parity, 8 bit char: receive interrupts enabled*/

 

and have an interrupt handler:

 

extern "C" void LPUART1_IRQHandler (void){

// UART RECEIVE

S32_NVIC->ICPR[LPUART1_NIPR_ADDR] = 1 << (LPUART1_IRQ % 32); /* clr any pending IRQ*/

   if((LPUART1->STAT & LPUART_STAT_RDRF_MASK)>>LPUART_STAT_RDRF_SHIFT==1)

   {

      lpuart1_receive = LPUART1->DATA;

   }

}

 

but am not seeing an interrupt triggered when the receive buffer flag is full; and then it overruns.

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