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QN9021 current consumption in Deep Sleep mode?

Question asked by rodri on May 15, 2017
Latest reply on May 25, 2017 by Gerardo Rodríguez

Hi,

 

I am working with QN9021 in SOC Mode, implementing a Quintic private profile in Server Role.

 

The highlights of my project configuration are:

driver_config.h :

#define __AHB_CLK       CLK_32M /*!< AHB clock frequency */
#define __APB_CLK       CLK_32M /*!< APB clock frequency */
#define __BLE_CLK       CLK_16M /*!< BLE clock frequency */

 

usr_config.h :

#define CFG_DC_DC
#define CFG_DEEP_SLEEP
#define CFG_BLE_SLEEP

 

Hardware design:

  • The hardware I am working with is a propietary one (it is not a evaluation kit) and its power supply is set in such a way VDD and VCC are connected and supplied with same power supply (3V on board).
  • An external 32.768 KHz crystal is connected to XTAL1_32K and XTAL2_32K  pins of QN9021
  • An external 32MHz crystal is connected to XTAL1 and XTAL2 pins of QN9021
  • QN9021 is being driven by a master MCU through SPI bus. Before entering sleep mode, master MCU is setting CLK and MOSI lines to '0'.
  • QN9021 chip select line is connected to 3V through a pull-up resistor (100K) and so, before entering sleep mode, master MCU is setting that line to '1'
  • QN9021 Reset line is held up ('1') by master MCU.

 

 

Firmware:

I can see, debugging the board that program is entering deep sleep mode (then, generating a interrupt in a GPIO will wake the device up).

 

Finally, the question is:

How can I achieve the 2uA of current consumption in deep sleep mode?? Because, with settings mentioned above, I am getting around 60uA and I have tried different options (QN_32K_LOW_POWER_MODE_EN = TRUE and FALSE,  CFG_DC_DC defined and commented, etc) and can not decrease QN9021 power consumption.

 

Thank you in advance!

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