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PXS3020 RANDOM BOOT UP ISSUE

Question asked by ramesh marichamy on Jan 22, 2017
Latest reply on Feb 3, 2017 by Lukas Zadrapa

Hi

I am using PXS3020 series micro controller in one of my application. I am operating it in external VREG mode.

The delay between 3.3V HV IO and 1.2V LV voltages is almost 6-10ms. (3.3V comes first and 1.2V is delivered later)Attached image for your reference.

I am driving the RESET_SUP pin (Pin no.AC20) using a open drain buffer which is reset by an external reset source. I have a pull up at open drain buffer output to 3.3V. Since my 3.3V rises first, the RESET_SUP releases before 1.2V.

 

I have around 5 modules which is working fine without any issues. But one of the module boots randomly during power up.

While debugging , I could see a statement in the datasheet that RESET_SUP not be released unless VDD_LV_xxx is within its valid range of operation. But the micro controller core starts working only after all voltage rails are up.

Will this could be the reason? what is the tech. reason for the statement. if RESET_SUP could be issue, why my other modules didn't have any issues so far past 2 years.

Please assist me in resolving the issue.

 

Regards,

Ramesh.M

 

 

I am using PXS3020 series micro controller in one of my application. I am operating it in external VREG mode.
The delay between 3.3V HV IO and 1.2V LV voltages is almost 6-10ms. (3.3V comes first and 1.2V is delivered later)Attached image for your reference.
I am driving the RESET_SUP pin (Pin no.AC20) using a open drain buffer which is reset by an external reset source. I have a pull up at open drain buffer output to 3.3V.
Since my 3.3V rises first, the RESET_SUP releases 6-8ms before 1.2V.
I have around 5 modules which is working fine without any issues even during extreme ambient temperatures. But one of the module boots randomly during power up.
While debugging , I could see a statement in the datasheet that RESET_SUP not to be released unless VDD_LV_xxx is within its valid range of operation. what is the tech. reason for the statement?.
If RESET_SUP could be issue, why my other modules didn't have any issues. is there a chance for the modules to work by not following the above condition?.
Please could you explain me is there by any chance the controller can be made working without this reset_sup?. Also could you brief how it could have worked so far?
Though theoretically the sequencing conditions are not met, practically it is working without any issues even during extreme ambient temperatures.
Please assist me in resolving the issue.
I have attached the image for your reference.
Regards,
Ramesh.M###@

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