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Choice of ECC strength in gpmi-nand driver

Question asked by Austin Phillips on Jan 19, 2017
Latest reply on Jun 13, 2017 by Arnout Diels



I'm using the the Linux BSP gpmi-nand.c driver from git://, tag rel_imx_4.1.15_1.2.0_ga with a Micron NAND MT29F4G08ABADAWP which has 2K + 64bytes OOB pages, and reports a minimum ECC strength of 4 bits per 512 byte data block.


The legacy gpmi-nand layout (fsl,legacy-bch-geometry [See Legacy gpmi-nand layout device tree option not handled correctly]) results in an ECC strength to be chosen as 8 bits.  The newer default BCH layout chooses an ECC of 4, which is minimum reported ECC strength required by the NAND part.


I'm curious as to why the default ECC strength for the NAND driver would be less than what could be supported by the available space in the part?


ie. With 2K + 64OOB pages, there is sufficient space to store ECC with 8 bit strength, so what is the reason the layout was changed from the legacy version (8 bit) to prefer a lower strength ECC (4 bit) by the newer layout?


Thank you