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i.MX7D SABRE GIC FIQ interrupt priority setting

Question asked by Joseph Heath on Dec 12, 2016
Latest reply on Jan 3, 2017 by jimmychan

Evaluating i.MX7D as next gen platform for motion control solution.  Existing solution uses i.MX35 FIQ for FPGA servicing/comms with <5us latency servicing the FIQ.  On the i.MX7D SABRE-SD I enabled multiple Group support on GIC (Group 0/Group 1 interrupts),  configured such that a single interrupt (96) is Group 0 and tied to a GPIO input pin.  Another GPIO pin is used for output.  Stimulus-response cycle is measured using external logic analyzer.  Observing high jitter with response intervals ranging from 1us to ~60us.

 

Dumped interrupt priority registers and see this:

HW addr   mmap addr   value

0x31001400  (0x76f10400) 0xa0a0a0a0
0x31001404  (0x76f10404) 0xa0a0a0a0
0x31001408  (0x76f10408) 0xa0a0a0a0
0x3100140c  (0x76f1040c) 0xa0a0a0a0
0x31001410  (0x76f10410) 0x00000000 - SGIs?
0x31001414  (0x76f10414) 0x00000000
0x31001418  (0x76f10418) 0xa0a0a000
0x3100141c  (0x76f1041c) 0xa0a0a0a0
0x31001420  (0x76f10420) 0xa0a0a0a0
0x31001424  (0x76f10424) 0xa0a0a0a0
0x31001428  (0x76f10428) 0xa0a0a0a0
0x3100142c  (0x76f1042c) 0xa0a0a0a0
0x31001430  (0x76f10430) 0xa0a0a0a0
0x31001434  (0x76f10434) 0xa0a0a0a0
0x31001438  (0x76f10438) 0xa0a0a0a0
0x3100143c  (0x76f1043c) 0xa0a0a0a0
0x31001440  (0x76f10440) 0xa0a0a0a0
0x31001444  (0x76f10444) 0xa0a0a0a0
0x31001448  (0x76f10448) 0xa0a0a0a0
0x3100144c  (0x76f1044c) 0xa0a0a0a0
0x31001450  (0x76f10450) 0xa0a0a0a0
0x31001454  (0x76f10454) 0xa0a0a0a0
0x31001458  (0x76f10458) 0xa0a0a0a0
0x3100145c  (0x76f1045c) 0xa0a0a0a0
0x31001460  (0x76f10460) 0xa0a0a020 - IRQ 96?
0x31001464  (0x76f10464) 0xa0a0a0a0
0x31001468  (0x76f10468) 0xa0a0a0a0
0x3100146c  (0x76f1046c) 0xa0a0a0a0
0x31001470  (0x76f10470) 0xa0a0a0a0
0x31001474  (0x76f10474) 0xa0a0a0a0
0x31001478  (0x76f10478) 0xa0a0a0a0
0x3100147c  (0x76f1047c) 0xa0a0a0a0
0x31001480  (0x76f10480) 0xa0a0a0a0
0x31001484  (0x76f10484) 0xa0a0a0a0
0x31001488  (0x76f10488) 0xa0a0a0a0
0x3100148c  (0x76f1048c) 0xa0a0a0a0
0x31001490  (0x76f10490) 0xa0a0a0a0
0x31001494  (0x76f10494) 0xa0a0a0a0
0x31001498  (0x76f10498) 0xa0a0a0a0
0x3100149c  (0x76f1049c) 0xa0a0a0a0

 

Attempted to modify these register settings but the block listed above as 0x31001410-0x31001414 appears to be protected.  I modified code in irq-gic.c::gic_cpu_init() (similar code in irq-gic-common.c) to set these priority values

        // force SGI/PPI to lower priority
        for (i = 0; i < 32; i += 4)
        {
            u32 val;
            writel_relaxed(0x80808080, //GICD_INT_DEF_PRI_X4,
                        dist_base + GIC_DIST_PRI + i * 4 / 4);
            val = readl_relaxed(dist_base + GIC_DIST_PRI + i * 4 / 4);
            printk("Updated priority for entry %d is 0x%0x\n", i, val);
        }

 

Here's what ends up in the syslog:
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 0 is 0x80808080
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 4 is 0x80808080
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 8 is 0x80808080
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 12 is 0x80808080
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 16 is 0x0
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 20 is 0x0
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 24 is 0x80808000
Dec 31 16:00:08 iMX7D-SABRESD kernel: Updated priority for entry 28 is 0x80808080

 

What's it take to change the SGI/PPI interrupt priorities?

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