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I2C: delay required between setting RSTA and write to D?

Question asked by Jan Rychter on Oct 18, 2016
Latest reply on Oct 19, 2016 by Paddock

Is there a required delay between setting a repeat start condition and writing to the D register?

 

The reason I'm asking is because I have code that is misbehaving. After a repeated start, the next address byte gets mangled unless I insert a delay loop before writing to the D register.

 

I'm additionally puzzled because this is code that I used successfully before. I am now running it on a KL03 and testing on a FRDM-KL03Z board.

 

Please see the attached scope screenshots. One shows a correct I2C sequence: W: 3A 0D, repeat start, R: 3B 1A. The other shows what happens if I remove the little delay: after a repeat start condition the next address byte gets transmitted as 0x0d (incidentally 0x0d is the previous byte that was transmitted before setting RSTA).

Correct sequence (delay inserted)

 

Incorrect behavior (delay removed)

 

This is the full code and the line where the delay needs to be inserted: https://github.com/jwr/kinetis_i2c/blob/master/i2c.c#L207 (e.g. just before line 207, the write to the D register).

 

I found experimentally that a loop like this:

 

for(delay_counter=0; delay_counter < 18; delay_counter++) {
__asm("NOP");
}

will fix the problem. Smaller number of iterations does not fix the problem.

 

I am running with the default clocks and mult=2, icr=0x17, in case it matters (to get about ~50kHz I2C), but different speeds don't seem to change much. Also, the workaround for issue 6070 (errata for mask 1N96F) doesn't help.

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