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Clock PLL discipline using external 10MHz signal

Question asked by adongare@cmu.edu Dongare on Sep 24, 2016
Latest reply on Sep 26, 2016 by Mark Butcher

I'm using a MK22FN512VLH12 chip clocked by an 8MHz crystal oscillator. For my current application, I have an external 10MHz reference signal and 1PPS signal available from a GPS-disciplined clock. My current PCB is based on the design of the FRDM-K22 board and I am using the KDS + KSDK environment for firmware development. Is there a way to discipline the PLL on the Kinetis chip (the one which generates the main 80MHz or 120MHz clock) using the 10MHz reference so that the microcontroller belongs to the same clock domain.

 

If necessary, I can make quick connections to any required pins using wire wrap for testing out any solutions.

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