Discussion created by ROBERTO BERNER on Jun 11, 2008
Latest reply on Jun 23, 2008 by ROBERTO BERNER
Hello friends !

There are some cases in which using the timer gets hard for me. I've been using timers since the 68HC11 times but sometimes trying to make it work in simple tasks, combining two or three interrupts ( Input Capture, PWM Output Compare and Overflow ) all combined, things don't go right and the results are weird.

Please correct me if I'm wrong, but for me the center issue is the way the timer is designed and know the working rules exactly. Generally the problem comes when trying to set an Output Compare value that is different from the previous used value, to generate an interrupt and also to abtain an output signal from the associated timer pin.  I would like to know  the rules. When can I program a new valid value related to the timer TCNT overflow without missing cycles  ? I have read many documents and application notes, including the datasheet for the M9S08QG8 ( in my last application ) and it say little about the timer rules. In older chip manuals such as the MC68HC908 line , there was advice about missing complete ( one or even two full timer cycles ) whenever the value of the output compare was changed before the main counter reached its  overflow ( FFFF -> 0000 ).

Some questions here to be more precise in my questions:

1. is it correct ( and "neat" ) to stop and completely reset the timer to ensure a clean, new Output Compare cycle ?
2. can the next Output Compare value be programmed and be effectively valid even if there was no Overflow between these changes ?
3. is it mandatory to center all the operation in the Overflow event to get precise Output Compares without losing cycles or having erratic behaviour ?
4. is there some complete literature about these timer issues that I could read ?

Thank you in advance