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Spansion QSPI S25FL256 in Vybrid VF65GS10

Question asked by Andreas Lie on Jul 8, 2016
Latest reply on Aug 24, 2016 by Karina Valencia Aguilar

Hello.

 

We are trying to use the Spansion QSPI S25FL256 chip in our Vybrid VF65GS10 based design but are struggling to get QSPI to work with Linux. We cannot read nor write to the QSPI chip.

We are using Yocto and Timesys BSP to build our custom Linux BSP. (Kernel 3.0.15)

 

The QSPI chip is connected to QSPI0_A. We have no QSPI chips on either QSPI0_B, QSPI1_A or QSPI1_B.

We have verified that the clock runs at 33MHz as intended.

 

We have employed the same iomux settings in U-boot, and there communication (read/write) to the QSPI chip works fine.

 

During boot we encounter this error message: (line 02). Apart from that, there are no error messages.

 

FSL NFC MTD nand Driver 1.0
cannot support 17 opcode
m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
Creating 9 MTD partitions on "Spansion s25fl256s SPI Flash chip":
0x000000000000-0x000000080000 : "U-Boot"
0x000000080000-0x000000100000 : "Environment"
0x000000100000-0x000000200000 : "InitScripts"
0x000000200000-0x000000400000 : "hwApp"
0x000000400000-0x000000800000 : "FPGA_Main"
0x000000800000-0x000000c00000 : "FPGA_Backup"
0x000000c00000-0x000000e00000 : "CPU_Main"
0x000000e00000-0x000001000000 : "CPU_Backup"
0x000001000000-0x000001100000 : "Configuration"
mvf-qspi mvf-qspi.0: QSPI bus driver
DSPI: Coldfire master initialized

 

Iomuxing for the QSPI0 device;

 

#define MVF600_PAD79_PTD0_QSPI0_A_SCK                       
\

    IOMUX_PAD(0x013C, 0x013c, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

#define MVF600_PAD80_PTD1_QSPI0_A_CS0                       
\

    IOMUX_PAD(0x0140, 0x0140, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_OBE_IBE_ENABLE)

#define MVF600_PAD81_PTD2_QSPI0_A_D3                        
\

    IOMUX_PAD(0x0144, 0x0144, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

#define MVF600_PAD82_PTD3_QSPI0_A_D2                        
\

    IOMUX_PAD(0x0148, 0x0148, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

#define MVF600_PAD83_PTD4_QSPI0_A_D1                        
\

    IOMUX_PAD(0x014C, 0x014c, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

#define MVF600_PAD84_PTD5_QSPI0_A_D0                        
\

    IOMUX_PAD(0x0150, 0x0150, 1, 0x0000, 0, \
    PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

 

Chip settings in the board file;

 

static struct flash_platform_data s25fl256s_spi_flash_data = {
    .name = "Spansion s25fl256s SPI Flash chip",
    .parts = s25fl256s_partitions,
    .nr_parts = ARRAY_SIZE(s25fl256s_partitions),
    .type = "s25fl256s1",
};


static struct spi_board_info mvf_spi_board_info[] __initdata = {
    {
        /* The modalias must be the same as spi device driver name */
        .modalias = "m25p80",
        .max_speed_hz = 66000000,
        .bus_num = 0,
        .chip_select = 0,
        .platform_data = &s25fl256s_spi_flash_data,
    },
...

 

Any help would be very much appreciated.

Thanks in advance.

Regards

Andreas L.

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