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LS2085A: dts entry for PHY

Question asked by ramasubramaniansubramanian on Jun 17, 2016


We have a custom board based on LS2085A RDB.  In our design, we have a PHY less connection of XFI interface to FPGA as shown below.  The dual 10G PHY are connected to emdio2.  Can you please show an example dts definition for the below case.?  How to show fixed link in dpl dts and mdio PHY connection in fsl dts?