LPC 1769 Adressing

[lpcware]

Content originally posted in LPCWare by m3t4lukas on Sat Feb 04 02:52:30 MST 2012
Hey guys,

I'm new to the LPC 1769 and wanted to know if there's any chance to put bits for example into P0.1 (J6-10) or P0.2 (J6-21). Before I used to write programs for the 6502 in Assembler. There I can set or unset the outputs by having their address. Is there a chance to get the addresses for the J6-XX outputs to control them directly?

Thanks
Lukas

[lpcware]

Content originally posted in LPCWare by m3t4lukas on Thu Feb 09 05:44:38 MST 2012
Thanks! That was what I was looking for :) So reading a pinstate is also done with masking :)

Now I can concentrate on functionality :)

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Thu Feb 09 03:49:08 MST 2012
What are we talking about :confused: Simple input setup ?

See #2 of http://knowledgebase.nxp.com/showthread.php?t=2417

[lpcware]

Content originally posted in LPCWare by m3t4lukas on Thu Feb 09 03:35:53 MST 2012
Okay, writing is okay now, what about reading? I don't need an interrupt necessarily. I read chapter 8 and 9 from the manual, but honestly I don't understand half of it :(

What I need to do is a function as a kind of handler of the pins, just with read (returning HI or LOW), set HI (1) and set LOW (0).

Thanks
Lukas

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sat Feb 04 05:53:55 MST 2012
Writing windows stuff isn't very exciting, so a little diversion is convenient :)

[lpcware]

Content originally posted in LPCWare by ex-kayoda on Sat Feb 04 05:32:49 MST 2012
Working on a boring windows :mad: program today, so every diversion is welcome...

[lpcware]

Content originally posted in LPCWare by OXO on Sat Feb 04 05:18:00 MST 2012

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Quote: Zero
Page 122 :)

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You have way too much patience Mr 0

:D

[lpcware]

Content originally posted in LPCWare by m3t4lukas on Sat Feb 04 05:16:09 MST 2012
Thanks :)
My search tool didn't found it :P

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sat Feb 04 05:14:27 MST 2012
Page 122 :)

[lpcware]

Content originally posted in LPCWare by ex-kayoda on Sat Feb 04 05:12:43 MST 2012
Chapter '9.5 Register description' :rolleyes:

[lpcware]

Content originally posted in LPCWare by m3t4lukas on Sat Feb 04 05:08:16 MST 2012
I can't find this table 101 nowhere in the manual...

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sat Feb 04 03:41:32 MST 2012
Addresses are described in User Manual UM10360 :)

http://www.nxp.com/download/pip/LPC1769FBD100/user_manual

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Quote:

Table 101. GPIO register map (local bus accessible registers - enhanced GPIO features)
Generic
Name
Description Access Reset
value[1]
PORTn Register
Name & Address
FIODIR Fast GPIO Port Direction control register. This register
individually controls the direction of each port pin.
R/W 0 FIO0DIR - 0x2009 C000
FIO1DIR - 0x2009 C020
FIO2DIR - 0x2009 C040
FIO3DIR - 0x2009 C060
FIO4DIR - 0x2009 C080
FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to
port (done via writes to FIOPIN, FIOSET, and FIOCLR, and
reads of FIOPIN) alter or return only the bits enabled by zeros
in this register.
R/W 0 FIO0MASK - 0x2009 C010
FIO1MASK - 0x2009 C030
FIO2MASK - 0x2009 C050
FIO3MASK - 0x2009 C070
FIO4MASK - 0x2009 C090
FIOPIN Fast Port Pin value register using FIOMASK. The current state
of digital port pins can be read from this register, regardless of
pin direction or alternate function selection (as long as pins are
not configured as an input to ADC). The value read is masked
by ANDing with inverted FIOMASK. Writing to this register
places corresponding values in all bits enabled by zeros in
FIOMASK.
Important: if an FIOPIN register is read, its bit(s) masked with
1 in the FIOMASK register will be read as 0 regardless of the
physical pin state.
R/W 0 FIO0PIN - 0x2009 C014
FIO1PIN - 0x2009 C034
FIO2PIN - 0x2009 C054
FIO3PIN - 0x2009 C074
FIO4PIN - 0x2009 C094
FIOSET Fast Port Output Set register using FIOMASK. This register
controls the state of output pins. Writing 1s produces highs at
the corresponding port pins. Writing 0s has no effect. Reading
this register returns the current contents of the port output
register. Only bits enabled by 0 in FIOMASK can be altered.
R/W 0 FIO0SET - 0x2009 C018
FIO1SET - 0x2009 C038
FIO2SET - 0x2009 C058
FIO3SET - 0x2009 C078
FIO4SET - 0x2009 C098
FIOCLR Fast Port Output Clear register using FIOMASK. This register
controls the state of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has no effect. Only bits
enabled by 0 in FIOMASK can be altered.
WO 0 FIO0CLR - 0x2009 C01C
FIO1CLR - 0x2009 C03C
FIO2CLR - 0x2009 C05C
FIO3CLR - 0x2009 C07C
FIO4CLR - 0x2009 C09C

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Setting / resetting bits is described several times here :rolleyes:

http://knowledgebase.nxp.com/showthread.php?t=2463

This addressing stuff is done here by CMSIS, which includes a lot of structs (in LPC17xx.h) to access all registers :)

Another option is Bit-Banding, which is described here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4203.html

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Quote:
The Cortex-M3 processor has a feature known as "bit-banding". This  allows an individual bit in a memory-mapped mailbox or peripheral  register to be set/cleared by a single store/load instruction to an  bit-band aliased memory address, rather than using a conventional  read/modify/write instruction sequence.

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Sample: http://support.code-red-tech.com/CodeRedWiki/BitBanding?highlight=%28bit-banding%29