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How to put LPC1315 to deep sleep?

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How to put LPC1315 to deep sleep?

‎06-15-2016 07:14 PM
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by cararra on Fri Jun 14 08:46:29 MST 2013
How to put LPC1315 to deep sleep?

LPC1315/16/17/45/46/47 User manual
Rev. 4 — 12 March 2013

Instructions say
1. The PD bits in the PCON register must be set to 0x1
2...
:
7. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
8. use __WFI()

Problem is step 7. There is no SLEEPDEEP bit or SCR register.:confused:
The SCR is defined as scratchpad registers in the UART section.

Any ideas?
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‎06-15-2016 07:14 PM
242 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by cararra on Fri Jul 05 00:48:10 MST 2013
Quote: cararra
Thank you, that was 100% accurate.
I was searching the practically useless CMSIS files for the information
which is why I could not make head way.

Here is what it should have contained reading up the ARM Cortex M3 reference manual:

typedef struct {                            /*!< (@ 0xE000ED00) SCB registers structure          */
  __I  uint32_t CPUID;                         /*!< (@ 0xE000ED00) CPUID register read only */
  __IO uint32_t ICSR;                       /*!< (@ 0xE000ED04) Interrupt Control State Register      */
  __IO uint32_t VTOR;                           /*!< (@ 0xE000ED08) Vector Table Offset Register */
  __IO uint32_t AIRCR;                        /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
  __IO uint32_t SCR;                        /*!< (@ 0xE000ED10) System Control Register */
  __IO uint32_t CCR;                        /*!< (@ 0xE000ED14) Configuration and Control Register  */
  __IO uint32_t SHPR1;                      /*!< (@ 0xE000ED18) System Handler Priority Register 1 */
  __IO uint32_t SHPR2;                      /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
  __IO uint32_t SHPR3;                      /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
  __IO uint32_t SHCSR;                      /*!< (@ 0xE000ED24) System Handler Control and State Registser */
  __IO uint32_t CFSR;                       /*!< (@ 0xE000ED28) Configurable Fault Status Register */
  __IO uint32_t HFSR;                       /*!< (@ 0xE000ED2C) Hard Fault Status Register */
  __IO uint32_t DFSR;                /*!< (@ 0xE000ED30) Debug Fault Status Register */
  __IO uint32_t MMFAR;                        /*!< (@ 0xE000ED34) MemManage Fault Address Register */
  __IO uint32_t BFAR;                          /*!< (@ 0xE000ED38) Bus Fault Address Register */
  __IO uint32_t AFSR;                       /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */
  __I  uint32_t RESERVED0[0x40];            /*!< (@ 0xE000ED40) reserved for CPUID registers */
  __I  uint32_t RESERVED1[0x02];            /*!< (@ 0xE000ED80) reserved */
  __IO uint32_t CPACR;                      /*!< (@ 0xE000ED88) CoProcessor Access Control Register */
  __I  uint32_t RESERVED2[0x01];            /*!< (@ 0xE000ED8C) reserved */
} LPC_SCB_Type;

#define LPC_SCB_BASE             (0xE000ED00)

#define LPC_SCB                  ((LPC_SCB_Type           *) LPC_SCB_BASE)


Using above, entering the command

LPC_SCB->SCR = 0x02;

Will put the device to sleep.

I tried different modes of sleep. The deep sleep gives me 7.5mA at 2MHz and 5mA
when its in deep sleep. This is way off the mark.

I am reading the manual as best as I can, but I am lost as to why the unit still
drains nearly 5mA when its supposed to be in deep sleep.
The power chip drains 0.5mA and it has been subtracted already.
This is purely the CPU drain on a prototyping board without any additional loading.

Any ideas anyone what else I must do to get power drain into the <1mA region for an LPC1315?


The reason why the CPU drains 5mA despite being in deep sleep mode is that the GPIO pins, even if nothing connected must be turned into inputs.

:mad::mad::mad:

Totally useless feature this deep sleep I thought at first.

Then it turns out the GPIO pins have weak pull ups and pull downs that can be programmed. Then if I connect the CPU to FET inputs, I can control the state of the FET by programming in the weak pull up or pull down despite the IO port being an input!!!!

The circuit diagram of the GPIO pins is in page 32 LPC1315/16/17/45/46/47
summary data sheet. It works as well.:p
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‎06-15-2016 07:14 PM
242 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by cararra on Mon Jun 17 08:40:19 MST 2013
Quote: cfb
The SCR (System Control Register) is defined in the Cortex-M3 documentation. Refer to pages B3-718/9 in the Arm v7-M Architecture Reference Manual (ARM DDI 0403D).

The address of SCR is 0xE000ED10 and SLEEPDEEP is bit 2.

Another useful reference is section 14.2 Power Management in Joseph Yiu's book "The definitive guide to the ARM CORTEX-M3".



Thank you, that was 100% accurate.
I was searching the practically useless CMSIS files for the information
which is why I could not make head way.

Here is what it should have contained reading up the ARM Cortex M3 reference manual:

typedef struct {                            /*!< (@ 0xE000ED00) SCB registers structure          */
  __I  uint32_t CPUID;                         /*!< (@ 0xE000ED00) CPUID register read only */
  __IO uint32_t ICSR;                       /*!< (@ 0xE000ED04) Interrupt Control State Register      */
  __IO uint32_t VTOR;                           /*!< (@ 0xE000ED08) Vector Table Offset Register */
  __IO uint32_t AIRCR;                        /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
  __IO uint32_t SCR;                        /*!< (@ 0xE000ED10) System Control Register */
  __IO uint32_t CCR;                        /*!< (@ 0xE000ED14) Configuration and Control Register  */
  __IO uint32_t SHPR1;                      /*!< (@ 0xE000ED18) System Handler Priority Register 1 */
  __IO uint32_t SHPR2;                      /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
  __IO uint32_t SHPR3;                      /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
  __IO uint32_t SHCSR;                      /*!< (@ 0xE000ED24) System Handler Control and State Registser */
  __IO uint32_t CFSR;                       /*!< (@ 0xE000ED28) Configurable Fault Status Register */
  __IO uint32_t HFSR;                       /*!< (@ 0xE000ED2C) Hard Fault Status Register */
  __IO uint32_t DFSR;                /*!< (@ 0xE000ED30) Debug Fault Status Register */
  __IO uint32_t MMFAR;                        /*!< (@ 0xE000ED34) MemManage Fault Address Register */
  __IO uint32_t BFAR;                          /*!< (@ 0xE000ED38) Bus Fault Address Register */
  __IO uint32_t AFSR;                       /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */
  __I  uint32_t RESERVED0[0x40];            /*!< (@ 0xE000ED40) reserved for CPUID registers */
  __I  uint32_t RESERVED1[0x02];            /*!< (@ 0xE000ED80) reserved */
  __IO uint32_t CPACR;                      /*!< (@ 0xE000ED88) CoProcessor Access Control Register */
  __I  uint32_t RESERVED2[0x01];            /*!< (@ 0xE000ED8C) reserved */
} LPC_SCB_Type;

#define LPC_SCB_BASE             (0xE000ED00)

#define LPC_SCB                  ((LPC_SCB_Type           *) LPC_SCB_BASE)


Using above, entering the command

LPC_SCB->SCR = 0x02;

Will put the device to sleep.

I tried different modes of sleep. The deep sleep gives me 7.5mA at 2MHz and 5mA
when its in deep sleep. This is way off the mark.

I am reading the manual as best as I can, but I am lost as to why the unit still
drains nearly 5mA when its supposed to be in deep sleep.
The power chip drains 0.5mA and it has been subtracted already.
This is purely the CPU drain on a prototyping board without any additional loading.

Any ideas anyone what else I must do to get power drain into the <1mA region for an LPC1315?
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‎06-15-2016 07:14 PM
242 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by cfb on Mon Jun 17 05:16:20 MST 2013
The SCR (System Control Register) is defined in the Cortex-M3 documentation. Refer to pages B3-718/9 in the Arm v7-M Architecture Reference Manual (ARM DDI 0403D).

The address of SCR is 0xE000ED10 and SLEEPDEEP is bit 2.

Another useful reference is section 14.2 Power Management in Joseph Yiu's book "The definitive guide to the ARM CORTEX-M3".
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‎06-15-2016 07:14 PM
242 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by cararra on Mon Jun 17 03:20:24 MST 2013
Quote: cararra
How to put LPC1315 to deep sleep?

LPC1315/16/17/45/46/47 User manual
Rev. 4 — 12 March 2013

Instructions say
1. The PD bits in the PCON register must be set to 0x1
2...
:
7. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
8. use __WFI()

Problem is step 7. There is no SLEEPDEEP bit or SCR register.:confused:
The SCR is defined as scratchpad registers in the UART section.

Any ideas?



I tried singing a lullaby - noo good! :o

Then I tried to set the PD bit in PCON although that is labeled as PM bits
on page 45. The instructions for deep sleep starts on page 38.

Anyone got a clue here what is supposed to be happening?:eek:
A couple of lines of sample code would be immense help.

Otherwise please escalate - more senior engineers may have to add their input.
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