pll formula

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Tue Apr 27 11:03:23 MST 2010
Is the pll formula this?

CCO = CLK_IN*M*P*2
FCLK = CCO/P*2

What are the recommended CCO frequency ranges for LPC11XX?

[lpcware]

Content originally posted in LPCWare by gbm on Fri Apr 30 10:17:19 MST 2010
While experimenting with PLL I thought about increasing the frequency of PLL and using > 1 divider for AHBCLK and other clocks. I started by checking frequency limits in manual and data sheet. Guess what were the results:

CPU/AHB clock max. frequency: not specified
Main Clock (PLL output) max. frequency: not specified

... or maybe, as previously, I am too dumb to find it.

Please help.

[lpcware]

Content originally posted in LPCWare by NXP_USA on Thu Apr 29 09:50:45 MST 2010

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Quote: gbm
Thanks a lot. Now everything is clear.

... And I thought that after 20+ years of hardware and firmware design I already knew how to read manuals... I simply overlooked section 3.9, searching for the information in 3.3 and register description to no avail. I'm not fluent at PLLs, but honestly I suspected that the role of this divisor is something like it is in reality.

Meanwhile I tuned the startup code, getting  to < 700 bytes of memory usage for PWM variable blinker.

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You might want to look at an example called usbhid_rom_tiny in the C:\nxp\lpcxpresso_3.3\Examples\LPC1000\LPC13xx\1343examples.zip example package. It ends up using about 400 bytes of flash memory to implement a USB device that controls the LED. Check the readme.txt in the project for details.

[lpcware]

Content originally posted in LPCWare by NXP_USA on Thu Apr 29 09:41:57 MST 2010

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Quote: rkiryanov
Of cource, it does not affect. The formula is

Fclkout = M × Fclkin

user.manual.lpc1111.lpc1112.lpc1113.lpc1114.pdf, page "38 of 330"

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Here is a spreadsheet for experimenting with the values to set up the PLL. It should warn of incorrect values and will calculate the hex value to set up the PLL ratio register.

[lpcware]

Content originally posted in LPCWare by gbm on Thu Apr 29 06:54:32 MST 2010
Thanks a lot. Now everything is clear.

... And I thought that after 20+ years of hardware and firmware design I already knew how to read manuals... I simply overlooked section 3.9, searching for the information in 3.3 and register description to no avail. I'm not fluent at PLLs, but honestly I suspected that the role of this divisor is something like it is in reality.

Meanwhile I tuned the startup code, getting  to < 700 bytes of memory usage for PWM variable blinker.

[lpcware]

Content originally posted in LPCWare by rkiryanov on Thu Apr 29 06:33:38 MST 2010

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Quote: gbm
I tried changing the divisor values (bits 6..5 of PLL control reg) with no effect on chip clock speed.

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Of cource, it does not affect. The formula is

Fclkout = M × Fclkin

user.manual.lpc1111.lpc1112.lpc1113.lpc1114.pdf, page "38 of 330"

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Quote:
To select the appropriate values for M and P, it is recommended to follow these steps:
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = Fclkout / Fclkin.
3. Find a value so that FCCO = 2 × P × Fclkout.
4. Verify that all frequencies and divider values conform to the limits specified in Table 8.

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[lpcware]

Content originally posted in LPCWare by gbm on Thu Apr 29 06:25:28 MST 2010
I encountered exactly the same problem yesterday, while fiddling with my just-received LPCExpresso board. The description of PLL in User's Manual is highly incomplete and probably false. I tried changing the divisor values (bits 6..5 of PLL control reg) with no effect on chip clock speed. Changing the primary divisor (bits 4..0 of PLL control register affects the clock frequency as expected. Looks like the output frequency is simply (<bits 4..0>) +1 * input freq. I succesfully ran the uC at 12, 24 and 48 MHz by changing bits 4..0.
Also, the CMSIS sources suggest that bits 6 and 5 do not influence the final frequency. Definitely some important information is missing from manual.

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Wed Apr 28 17:16:04 MST 2010
Then the 0x23 value that is the value in CMSIS is out of range.

[lpcware]

Content originally posted in LPCWare by rkiryanov on Tue Apr 27 23:44:07 MST 2010
user.manual.lpc1111.lpc1112.lpc1113.lpc1114.pdf, last line of page "36 of 330":

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Quote:
The CCO frequency range is 156 MHz to 320 MHz.

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