Help with understanding PLL0

[lpcware]

Content originally posted in LPCWare by micro9000 on Sat Jul 06 21:22:11 MST 2013
I looked over the PLL0 section (section 4.5) in the user manual. I have the LPC1764 and would like to ensure that it is running at 100MHz and I would also like to use USB at 48MHz.

From my understanding, the process to get 100MHz is as follows:

XTAL or Fin = 20MHz
Target FOSC = 100MHz

FCCO = 4 x 100MHz => 400MHz

M = (FCCO x N) / (2xFin) => (400MHz x 1) / (2 x 20MHz) => 400MHz/40MHz => 10

M-1 = 10-1 => 9
N-1 = 1-0=> 0

So, after doing the above calculations, I would put 0x09 into the PLL0CFG register. However, I was thankfully assisted and given a value beforehand. This was as follows:

Under the CMSISv2p00_LPC17xx project and within the source file system_LPC17xx.c I changed

#define PLL0CFG_Val 0x00050063 to  #define PLL0CFG_Val  0x00090063

I think I understand where the 9 comes from (from the M-1 that I calculates above) and corresponds to bits 16-23 AKA NSEL0. But, I don't understand where the 63 comes from (I'm looking at table 20 on pg. 37). It says MSEL0 bits 0-14 and it handles the "PLL0 Multiplier value "M" in PLL0 frequency calculations, which I though was 9 and not 63.

In addition, I took a look at section 4.7 and I'm not sure how to manipulate that register. If anyone could assist me with further understanding the PLL0 and CCLK config registers it would be much appreciated. Thank you.

[lpcware]

Content originally posted in LPCWare by R2D2 on Mon Jul 08 04:41:52 MST 2013
SystemInit is used to init your system from default (like IRC...). Therefore I would avoid to use it again after a system is running with valid PLL configuration.
If you want to change something later, just copy the section of SystemInit and read UM carefully.

SystemCoreClockUpdate is just updating SystemCoreClock value and changing no registers.

[lpcware]

Content originally posted in LPCWare by micro9000 on Sun Jul 07 17:44:09 MST 2013
Thanks, that's what I was thinking since the delay using loops didn't seem that accurate. Also, can you call SystemInit(); and SystemCoreClockUpdate(); in main to update PLL settings during runtime?

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Jul 07 17:30:56 MST 2013

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Quote: micro9000
...higher oscillator value gives you a lower M/N, which according to the datasheet is better  (not too sure)?

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No, why?

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Quote: micro9000
For delays I used a for loop that goes to 0 to 2 million. Assuming it is 1 clock cycle per instruction is correct to also assume the the total delay that this for loop is creating is 2e6 * 10e-9 => 20ms?

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Forget loops, use SysTick (Sample in Example folder...). M3 has a 3-stage pipeline, which can speed up things.

Also different Optimizations can create different times (or optimize out your loop :)).

Therefore it's by far better to use a timer and SysTick is made for that purpose...

[lpcware]

Content originally posted in LPCWare by micro9000 on Sun Jul 07 16:50:55 MST 2013
Oh, whew :). I'll get a 12MHz oscillator, I just assumed that a higher oscillator value gives you a lower M/N, which according to the datasheet is better (not too sure)? Anyway I'll go and pick up a 12MHz resonator off of digikey and double check the default configuration and I should be good to go. Thanks again.

Just one more quick question (a bit off topic). For delays I used a for loop that goes to 0 to 2 million. Assuming it is 1 clock cycle per instruction is correct to also assume the the total delay that this for loop is creating is 2e6 * 10e-9 => 20ms?

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Jul 07 16:19:16 MST 2013

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Quote: micro9000
Sorry for the confusion, PBCLK = Peripheral bus clock. I see that there is a Peripheral clock divider and I was just wondering if I needed to set anything further.

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Peripherals are clocked with PCLKSEL0 /PCLKSEL1 divider from CCLK.

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Quote: micro9000
So, with a 24MHz oscillator I can get an FCC0 of 480MHz, but how do I  still get 100MHz? Is it not possible to have 100MHz w/ USB at 48MHz :( ?

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Standard crystal is 12MHz and therefore CMSIS default settings are creating a valid PLL0 / PLL1.

I don't understand why you want to use 24MHz, but anyway:

PLL0CFG_Val 0x00050063 is creating 100MHz from 12MHz crystal.

A simple way of changing that to a 24MHz setup could be to double the divider or to halve the multiplier ;)

[lpcware]

Content originally posted in LPCWare by micro9000 on Sun Jul 07 14:38:56 MST 2013
Sorry for the confusion, PBCLK = Peripheral bus clock. I see that there is a Peripheral clock divider and I was just wondering if I needed to set anything further.

I find it sort off odd that USB isn't possible with a 20MHz oscillator as Microchips PICs can do it just fine, but if that's the case then I'll have to grab a 24MHz oscillator. Anyway, thanks for the info I'll have to look it over more.

EDIT:
So, with a 24MHz oscillator I can get an FCC0 of 480MHz, but how do I still get 100MHz? Is it not possible to have 100MHz w/ USB at 48MHz :( ?

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Jul 07 14:12:05 MST 2013

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Quote: micro9000
From what I gathered the output to PLL0 is 400MHz and CCLK must be set to 3 (but is actually 3+1=4) to get 400MHz/4 => 100MHz. So, is the CPU is indeed running at 100MHz, right?

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UM:

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Quote:
The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1

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So CCLKCFG_Val = 3 is correct to divide by 4.

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Quote:

1. Do I also need to configure the PBCLK?

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:confused: Is this something religious?

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Quote:

2. Can I use PLL1 to get 48MHz for the USB clock without any addition  external circuitry or do I have to leach off of PLL0 for USB?

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No.

UM:

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Quote:

4.6.9 Procedure for determining PLL1 settings
The PLL1 configuration for USB may be determined as follows:
1. The desired PLL1 output frequency is USBCLK = 48 MHz.
2. Choose an oscillator frequency (FOSC). USBCLK must be the whole (non-fractional) multiple of FOSC meaning that the possible values for FOSC are 12 MHz, 16 MHz, and 24 MHz.

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PLL1 Setup is different (like at LPC13 or LPC11):

USBCLK = M × FOSC

And no,  setting M to 2.4 is not possible.

If it wasn't clear for you why no one is using a 20MHz crystal, there's your answer :)

[lpcware]

Content originally posted in LPCWare by micro9000 on Sun Jul 07 12:47:23 MST 2013
Oh, okay, that makes a bit more sense. I now understand a bit more about the line of code you helped me out with the other day :). From what I gathered the output to PLL0 is 400MHz and CCLK must be set to 3 (but is actually 3+1=4) to get 400MHz/4 => 100MHz. So, is the CPU is indeed running at 100MHz, right?

I also have a few more questions if you don't mind helping me out a bit more.

1. Do I also need to configure the PBCLK?
2. Can I use PLL1 to get 48MHz for the USB clock without any addition external circuitry or do I have to leach off of PLL0 for USB?
3. I see that there is a set sequence (I found some sample code on it) to set up the PLL0. Is this only if I want to change FOSC during runtime? (I'm looking at 4.5.13 PLL0 setup sequence pg. 46 in the user manual).

Thanks again.

EDIT:
Upon further inspection of system_LPC17xx.c I see that under "SystemInit" towards the bottom, the PLL setup sequence for PLL0 and PLL1 is carried out and utilizes the configuration values modified towards the top. Pretty cool.

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Jul 07 01:23:04 MST 2013
What's not clear there?

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Quote:

4.5.1 PLL0 operation
The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 6 through 512, plus additional values listed in Table 21. The resulting frequency
must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO
output by the value of M, then using a phase-frequency detector to compare the divided
CCO output to the multiplier input. The error value is used to adjust the CCO frequency.

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Quote:

The PLL0 output frequency (when PLL0 is both active and connected) is given by:
FCCO = (2 × M × FIN) / N
PLL inputs and settings must meet the following:
• FIN is in the range of 32 kHz to 50 MHz.
• FCCO is in the range of 275 MHz to 550 MHz.
The equation can be solved for other PLL parameters:
M = (FCCO × N) / (2 × FIN)
N = (2 × M × FIN) / FCCO
FIN = (FCCO × N) / (2 × M)

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If you start with 20MHz and want to get 100MHz there are just 2 calculations needed:

[B][COLOR=Red]1. Define a CPU Clock Configuration register (CCLKCFG)[/COLOR] [/B]value, that's usually 3.

So PLL0 output is divided by 4 (3+1) to create the CPU clock (CCLK).

      Now you know:  PLL0 should be 400MHz.
  
[COLOR=Red][B]2. Select M and M[/B][/COLOR] with:

      FCCO = (2 × M × FIN) / N => 400MHz = 40MHz * M / N => 10 = M/N
  
      So with M = 100 (0x64) and N = 10 (0x0A) you get  Mvalue = 0x63 and Nvalue = 9
  
      And a working value (surprise :)) is PLL0CFG_VAL = 0x00090063.

Perhaps it's irritating, but PLL0 is setting PLL0, not CPU clock.