lpcware

Help with understanding PLL0

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by micro9000 on Sat Jul 06 21:22:11 MST 2013
I looked over the PLL0 section (section 4.5) in the user manual. I have the LPC1764 and would like to ensure that it is running at 100MHz and I would also like to use USB at 48MHz.

From my understanding, the process to get 100MHz is as follows:

XTAL or Fin = 20MHz
Target FOSC = 100MHz

FCCO = 4 x 100MHz => 400MHz

M = (FCCO x N) / (2xFin) => (400MHz x 1) / (2 x 20MHz) => 400MHz/40MHz => 10

M-1 = 10-1 => 9
N-1 = 1-0=> 0

So, after doing the above calculations, I would put 0x09 into the PLL0CFG register. However, I was thankfully assisted and given a value beforehand. This was as follows:

Under the CMSISv2p00_LPC17xx project and within the source file system_LPC17xx.c I changed

#define PLL0CFG_Val 0x00050063 to  #define PLL0CFG_Val  0x00090063

I think I understand where the 9 comes from (from the M-1 that I calculates above) and corresponds to bits 16-23 AKA NSEL0. But, I don't understand where the 63 comes from (I'm looking at table 20 on pg. 37). It says MSEL0 bits 0-14 and it handles the "PLL0 Multiplier value "M" in PLL0 frequency calculations, which I though was 9 and not 63.

In addition, I took a look at section 4.7 and I'm not sure how to manipulate that register. If anyone could assist me with further understanding the PLL0 and CCLK config registers it would be much appreciated. Thank you.

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