**Content originally posted in LPCWare by micro9000 on Sat Jul 06 21:22:11 MST 2013**

I looked over the PLL0 section (section 4.5) in the user manual. I have the LPC1764 and would like to ensure that it is running at 100MHz and I would also like to use USB at 48MHz.

From my understanding, the process to get 100MHz is as follows:

XTAL or Fin = 20MHz

Target FOSC = 100MHz

FCCO = 4 x 100MHz => 400MHz

M = (FCCO x N) / (2xFin) => (400MHz x 1) / (2 x 20MHz) => 400MHz/40MHz => 10

M-1 = 10-1 => 9

N-1 = 1-0=> 0

So, after doing the above calculations, I would put 0x09 into the PLL0CFG register. However, I was thankfully assisted and given a value beforehand. This was as follows:

Under the CMSISv2p00_LPC17xx project and within the source file system_LPC17xx.c I changed

#define PLL0CFG_Val 0x00050063 to #define PLL0CFG_Val 0x00090063

I think I understand where the 9 comes from (from the M-1 that I calculates above) and corresponds to bits 16-23 AKA NSEL0. But, I don't understand where the 63 comes from (I'm looking at table 20 on pg. 37). It says MSEL0 bits 0-14 and it handles the "PLL0 Multiplier value "M" in PLL0 frequency calculations, which I though was 9 and not 63.

In addition, I took a look at section 4.7 and I'm not sure how to manipulate that register. If anyone could assist me with further understanding the PLL0 and CCLK config registers it would be much appreciated. Thank you.

Content originally posted in LPCWare by R2D2 on Sun Jul 07 01:23:04 MST 2013What's not clear there?

Quote:4.5.1 PLL0 operation

The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value

"N", which may be in the range of 1 to 256. This input division provides a greater number

of possibilities in providing a wide range of output frequencies from the same input

frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the

range of 6 through 512, plus additional values listed in Table 21. The resulting frequency

must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO

output by the value of M, then using a phase-frequency detector to compare the divided

CCO output to the multiplier input. The error value is used to adjust the CCO frequency.

Quote:The PLL0 output frequency (when PLL0 is both active and connected) is given by:

FCCO = (2 × M × FIN) / N

PLL inputs and settings must meet the following:

• FIN is in the range of 32 kHz to 50 MHz.

• FCCO is in the range of 275 MHz to 550 MHz.

The equation can be solved for other PLL parameters:

M = (FCCO × N) / (2 × FIN)

N = (2 × M × FIN) / FCCO

FIN = (FCCO × N) / (2 × M)

If you start with 20MHz and want to get 100MHz there are just 2 calculations needed:

[B][COLOR=Red]1. Define a CPU Clock Configuration register (CCLKCFG)[/COLOR] [/B]value, that's usually 3.

So PLL0 output is divided by 4 (3+1) to create the CPU clock (CCLK).

Now you know: PLL0 should be 400MHz.

[COLOR=Red][B]2. Select M and M[/B][/COLOR] with:

FCCO = (2 × M × FIN) / N => 400MHz = 40MHz * M / N => 10 = M/N

So with M = 100 (0x64) and N = 10 (0x0A) you get Mvalue = 0x63 and Nvalue = 9

And a working value (surprise :)) is PLL0CFG_VAL = 0x00090063.

Perhaps it's irritating, but PLL0 is setting PLL0, not CPU clock.