lpcware

Is SRAM Preserved in Various Sleep/Power Modes

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MikeSimmonds on Wed Apr 18 23:29:01 MST 2012
[FONT=Tahoma]I'm specifiaclly interested[/FONT] in the LPC1778 (208 pin) part.

[FONT=Tahoma]There are mentions of SRAM preservation for some of the modes, but no statement one way or the other for the rest.

Can anyone give a [I]definative[/I] chart for SRAM value retention for
  SLEEP,  DEEP SLEEP, POWER DOWN, DEEP POWER DOWN, and NOT POWERED (I can hope).

The reason is that I want to detect power fail (i.e. unit is unplugged from supply) and switch to a battery to maintain SRAM (if possible, the same battery used for the RTC).

Obviously, I want the lowest drain on the battery that preserves SRAM so that on next power up certain user data is still available. (I don't care about PLLs, peripheral state etc, but want RTC time/date, as I expect a subsequent POR.)

Note there will be up to 16K of data so the RTC backup registers are not suitable and due to change frequency, I cannot use flash/eeprom for storage.

[B]To Recap, what is the lowest power mode that preserves (main) SRAM?[/B]

Cheers, Mike


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