LPC_SYSCON->SYSTICKCLKDIV = 0x02; LPC_SSP->CR0 = 0x00C7; LPC_SSP->CPSR = 0x2; |
if (clk_speed == SSP_SLOW) /* (PCLK / (CPSDVSR — [SCR+1])) = (7,200,000 / (2 x [8 + 1])) = 400 KHz */ LPC_SYSCON->SSPCLKDIV = 10; /* Divided by 10 */ else /* (PCLK / (CPSDVSR — [SCR+1])) = (72,000,000 / (2 * [1 + 1])) = 18.0 MHz */ LPC_SYSCON->SSPCLKDIV = 1; /* Divided by 1 */ ... if (clk_speed == SSP_SLOW) { /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 8 */ LPC_SSP->CR0 = 0x0807; } else { /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 1 */ LPC_SSP->CR0 = 0x0107; } /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ LPC_SSP->CPSR = 0x2; |