The relation between EOT, SSD, and SSEL on LPC54102 ?????

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by okwh on Sat Dec 19 01:21:39 MST 2015
I need to send 24 bits out. 
first 8 bits in the first write to TXDATCTL without EOT. and then  send 4 bits  with EOT

In other word,  not allow  Deassert  (SSEL change)  between 8 and 16 bits.

I use STALLED state to judge first 8 bits has sent, and then send 16 bits. (is this right?)

but when I use  logic analyzer to check SPI signals, find  SSEL change (CS signal)  between 8 and 16 bits.!!

What's wrong with it?

I debuged step by step, sure cleared  EOT bit  in TXCTL before 8 bits, set it befor 16 bits,
and no SDD state after  8 bits.

so why are there  SSEL change sinal between 8 and 16 bits seen on logic analyzer ????

as I know , only when I set EOT,  then SSD and SSEL change generate after send.
when I clear EOT,  then  no SSD and no SSEL change generate after send.

but now when I clear  EOT, no SSD (with code debug) but have SEEL change  (with logic analyzer),