lpcware

Want to configure SPI0 as master & SPI1 as slave in one c program

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by bhoomil on Sat Jun 20 01:19:41 MST 2015
Hi everyone,
It is possible to configure SPI0 & SPI1 as master & slave on the same chip?
The problem is that master write the data but slave couldn't read the same. I'm beginner in lpc54102.
I was actually facing some problem by using this configuration.

Pin Muxing are as follows,

static void Init_SPIM_PinMux(void)
{
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 5, (IOCON_FUNC2 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP)); /* P1_5-SSEL1_0-CT32B1_MAT3 */
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 6, (IOCON_FUNC2 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP)); /* P1_6-SCK1-CT32B1_MAT2 */
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 7, (IOCON_FUNC2 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP)); /* P1_7-MOSI1-CT32B1_MAT2 */
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 8, (IOCON_FUNC2 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP)); /* P1_8-MISO1-CT32B1_MAT3 */
}

static void Init_SPIS_PinMux(void)
{
/* 1.3 = SPI0_SCK, 0.14 = SPI0_SSELN0, 0.12 = SPI0_MOSI, 1.4 = SPI0_MISO */
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 3,  (IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP));
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 14, (IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP));
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 12, (IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP));
Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 4,  (IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP));
}

My transfer function is doing following things,

while(1)
{
/* Populate some TX data and clear RX data */
for (i = 0; i < BUFFSENDSIZE; i++) {
tx16 = i + 1;
rx16 =  0;
}

/* Setup buffers and sizes, use select 0 for transfer */
mXfer.txBuff = tx16;
mXfer.txSz = BUFFSENDSIZE;
mXfer.rxBuff = NULL;
mXfer.rxSz = 0;
mXfer.sselNum = 0;
mXfer.flags = ROM_SPIM_FLAG_RXIGNORE;

/* Start transfer. Will return immediately */
ROM_SPIM_Transfer(spimHandle, &mXfer);

while (mXfer.status == ERR_SPI_BUSY) {
ROM_SPIM_TransferHandler(spimHandle);
}

/* Check status of the transfer */
if (mXfer.status != LPC_OK) {
DEBUGOUT("-Error performing transfer(master) = %x\r\n", mXfer.status);
}
else {
DEBUGOUT("-SPI1(Master) transfer completed: status = %x\r\n", mXfer.status);
for (i = 0; i < BUFFSENDSIZE; i++) {
DEBUGOUT("%04x %04x : ", tx16, rx16);
}
DEBUGSTR("\r\n");
}


/* Setup transfer buffers and maximum transfer sizes, no transfer flags */
sXfer.txBuff = NULL;
sXfer.txSz = 0;
sXfer.rxBuff = rx16;
sXfer.rxSz = BUFFSENDSIZE;
sXfer.flags = ROM_SPIS_FLAG_TXIGNORE;

/* Start transfer. Will return immediately */
ROM_SPIS_Transfer(spisHandle, &sXfer);

while (sXfer.status == ERR_SPI_BUSY) {
ROM_SPIS_TransferHandler(spisHandle);
}

/* Check status of the transfer */
if (sXfer.status != LPC_OK) {
DEBUGOUT("-Error performing transfer(slave) = %x\r\n", sXfer.status);
}
else {
DEBUGOUT("-SPI0(Slave) transfer completed: status = %x\r\n", sXfer.status);
for (i = 0; i < sXfer.txSent; i++) {
DEBUGOUT("%04x %04x : ", tx16, rx16);
}
DEBUGSTR("\r\n");
}
}

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