LPCOpen LPC1114 IOConfig question

[lpcware]

Content originally posted in LPCWare by ccrbs on Sat Jan 04 17:47:12 MST 2014
Hi,

I used LPCopen v1.03 for LPC11U14. It is OK for my board on KEIL MDK 4.7. Recently I changed to LPC1114 and study the LPCopen file on iocon_11XX.h. I found that the LPC_IOCON_T for LPC11XX define offset addr shifted 2 bits. Compared the LPC1114 Manual, offset addr number is correct, why shifte right 2 bits? Please advise the reason. Many thanks.

Best Regards,

Robert

here is the define in iocon_11XX.h


#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
typedef struct {/*!< LPC11AXX/LPC11UXX/LPC11EXX IOCON Structure */
__IO uint32_t  PIO0[24];
__IO uint32_t  PIO1[32];
} LPC_IOCON_T;

#else
/**
* @brief LPC11XX I/O Configuration register offset
*/
typedef enum CHIP_IOCON_PIO {
IOCON_PIO0_0 = (0x00C >> 2),
IOCON_PIO0_1 = (0x010 >> 2),
IOCON_PIO0_2 = (0x01C >> 2),
IOCON_PIO0_3 = (0x02C >> 2),
IOCON_PIO0_4 = (0x030 >> 2),
IOCON_PIO0_5 = (0x034 >> 2),
IOCON_PIO0_6 = (0x04C >> 2),
IOCON_PIO0_7 = (0x050 >> 2),
IOCON_PIO0_8 = (0x060 >> 2),
IOCON_PIO0_9 = (0x064 >> 2),
IOCON_PIO0_11 = (0x074 >> 2),

IOCON_PIO1_0 = (0x078 >> 2),
IOCON_PIO1_1 = (0x07C >> 2),
IOCON_PIO1_2 = (0x080 >> 2),
IOCON_PIO1_3 = (0x090 >> 2),
IOCON_PIO1_4 = (0x094 >> 2),
IOCON_PIO1_5 = (0x0A0 >> 2),
IOCON_PIO1_6 = (0x0A4 >> 2),
IOCON_PIO1_7 = (0x0A8 >> 2),
IOCON_PIO1_8 = (0x014 >> 2),
IOCON_PIO1_9 = (0x038 >> 2),
IOCON_PIO1_10 = (0x06C >> 2),
IOCON_PIO1_11 = (0x098 >> 2),

IOCON_PIO2_0 = (0x008 >> 2),
IOCON_PIO2_1 = (0x028 >> 2),
IOCON_PIO2_2 = (0x05C >> 2),
IOCON_PIO2_3 = (0x08C >> 2),
IOCON_PIO2_4 = (0x040 >> 2),
IOCON_PIO2_5 = (0x044 >> 2),
IOCON_PIO2_6 = (0x000 >> 2),
IOCON_PIO2_7 = (0x020 >> 2),
IOCON_PIO2_8 = (0x024 >> 2),
IOCON_PIO2_9 = (0x054 >> 2),
IOCON_PIO2_10 = (0x058 >> 2),
IOCON_PIO2_11 = (0x070 >> 2),

IOCON_PIO3_0 = (0x084 >> 2),
IOCON_PIO3_1 = (0x088 >> 2),
IOCON_PIO3_2 = (0x09C >> 2),
IOCON_PIO3_3 = (0x0AC >> 2),
IOCON_PIO3_4 = (0x03C >> 2),
IOCON_PIO3_5 = (0x048 >> 2),
} CHIP_IOCON_PIO_T;

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Wed Jan 08 16:39:51 MST 2014
I never used LPCOpen.

It appears to me as if the shift right by two corresponds with the basic type in the struct (4-byte size).
So if the enums are used for indexing REG, then the resulting offset is exactly the number left to the shift operator.

Honestly, I don't understand why everybody except me seems to like such headers. |(
I attached one file of my lpc800 lib. The offsets therein are more obvious IMHO.

I prefer writing things like:

GPIO.set0 = 2;

instead of cryptic bullsh!t like

GPIO->SO_MEANINGLESS [ GPIO_SET0 ] = 2;

Sorry.

[lpcware]

Content originally posted in LPCWare by ccrbs on Sat Jan 04 21:21:07 MST 2014
It look like to 32bits alian, is it right?

typedef struct {/*!< LPC11XX/LPC11XXLV/LPC11UXX IOCON Structure */
__IO uint32_t  REG[48];
} LPC_IOCON_T;

Another question: if I change the chip define in sys_config.h as following, is it to generate a lib for LPC1114? Or do I need to change other files for LPC1114?

/* Build for 11Uxx chip family */
//#define CHIP_LPC11UXX
/* Build for 11xx chip family */
#define CHIP_LPC11XXLV