4-bit Planar EL display timing restrictions

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by adampmtnw on Mon Jun 25 16:24:32 MST 2012
I am working on a demo to start incorporating the LPC1788 in one of our products. I'm using the LPC1788 and a Planar EL display. According to Planar no horizontal front or back porch is required. The 177x8x UM states on page 290 horizontal timing restrictions of a horz. back and front porch of 5 clock cycles due to DMA timing restrictions. A conflicting statement in the Vertical Sync. Pulse Width register description states "The number of horz. sync line must be small ... (program to zero) ..."

I am confused; is it possible to program the HFP and HBP to zero? I am currently unable to get anything to show on the EL display and I suspect this may be part of the issue.

Additional Info:
- 4-bit interface
- 1 bit per pixel
- 160 x 80 resolution

Thank you,