lpcware

Peripheral SRAM

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by ezharkov on Fri Aug 30 11:18:10 MST 2013
From UM10470:
0x2000 0000 - 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 - 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 - 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB)

Why the difference between bank 0 and bank 1? Why bank 0 is split into the "first" and "second" 8kB? Are those two 8kB sections on different ports or something?

Will a DMA transaction work with a block that starts in the first 8k and ends in the second 8k?
Will a DMA transaction work with a block that starts in the bank 0 and ends in the bank 1?

Thanks,
Eugene

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