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SSP in SPI slave mode: SSPx status register reports FIFO empty, but data lags 8 bytes behind

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MindBender on Thu Jul 30 05:24:36 MST 2015
I am using the SSP0 peripheral as a SPI slave, and I am experiencing a rather weird problem: When I write a byte of data to the Data Register and the SPI master is clocking the bus, the data byte comes out as the 9th byte on the bus.

When freshly started, the preceding 8 bytes all have a value of 0. When restarting in with the debugger, these 8 bytes have values of the not-yet-shown 8 bytes of the previous session. During the problem, the Status Register has a value of 0x00000003 all the time, indicating that the TX FIFO is empty.

My test is really simple: Write a single byte to the data register and have the SPI master read it. The first 8 times I read zeroes on the master and my scope, the 9th time I read the 1st data byte. If in that state the master reads again without writing an new data byte to the Data Register, the master reads de 1st data byte again. It is as if transmitted bytes always have to travel through the whole FIFO, regardless of it's filling grade.

This problem only occurs at SPI clock frequencies of 250kHz and higher. If I have the master clock the bus at 30kHz or 125kHz, data bytes come out immediately.

The manual writes that Clock Prescaler Register contents are irrelevant for SPI in slave mode. It Does not say something similar about the SCR field in Control Register 0, but those two are determining the SPI bit rate. However, configuring both for 8MHz SPI doesn't change anything in the situation; Neither 250kHz or 8MHz work properly.

Any ideas? Anybody had something similar? Or anybody has a working SPI slave @>=250kHz?

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