lpcware

LPC17xx packet over-written bit?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by doogul on Wed Jul 08 18:53:30 MST 2015
Hi there,

I've been working on my own USB device stack for the LPC1768. I'm making good progress on implementing all of the control transfers for EP0 (my device enumerates successfully on Windows), but one place in the register documentation has me confused.

In UM10360, section 11.12.13, there is an interesting comment in the "Clear Buffer" SIE command description about the returned data byte from the command:


Quote:
When bit 0 of the optional data byte is 1, the previously received packet was over-written by a SETUP packet. The Packet over-written bit is used only in control transfers. According to the USB specification, a SETUP packet should be accepted irrespective of the buffer status. The software should always check the status of the PO bit after reading the SETUP data. If it is set then it should discard the previously read data, clear the PO bit by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and again check the status of the PO bit.



This appears to be for handling a minor edge case where an existing control transfer is canceled because a new SETUP packet for a new control transfer arrived before I was finished with the first one.

My USB EP_SLOW interrupt handler always writes a 1 to the corresponding USBEpIntClr bit before it even starts reading the received packet data. It seems like if the PO bit had been set, it would already be cleared before I even did the clear buffer command that would read it out. During normal operation, am I supposed to be waiting until after I read the endpoint data and clear the buffer before I clear the endpoint interrupt? If I see the PO bit in the "clear buffer" result byte, am I supposed to write a 1 to the corresponding USBEpIntClr bit *again*, and then immediately try to read the SETUP packet data from the endpoint again without waiting for the EP_SLOW interrupt to fire again, or should I just exit and hope that another EP_SLOW interrupt comes in for the "replacement" setup packet?

The instructions in the datasheet don't provide a lot of clarity about the exact sequence of events. I don't understand exactly what I'm supposed to do when this happens. It's hard to test because I'm not sure I can get my computer to send such a sequence of packets. None of the example USB stacks for the LPC1768 that I've inspected look at the PO bit at all. I've done a ton of Googling and it appears that nobody ever talks about what to do in this case. Does anyone have any better details on exactly what I'm supposed to do, and/or how to test this particular sequence of packets?

Thanks for any insight!

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