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MCF5234: functionality of the interrupt controller

Question asked by sirlenzelot on Jun 7, 2016
Latest reply on Jul 7, 2016 by sirlenzelot


Hi All!

 

Dealing with interrupt service routines I ran into some questions. Maybe you can help?

 

1)

In 13.2.1.6 of the reference manual they say that you have to program the ICRnx registers with "unique and non-overlapping level and priority definitions".

In 13.3 they tell about prioritization between INTC0 and INTC1 and that INTC0 will be served first, if there are two interrupts with the same level and priority.

 

Am I right that I am allowed to have two interrupts with the same level and priority if they have different interrupt controllers?

 

2)

Maybe I missed it, but what is the correct time to clear the interrupt flags? At the beginning or at the end of the interrupt service routine?

 

3)

The MCF5234 supports nested interrupts. What happens if I clear the interrupt flag at the beginning of the ISR and before the ISR has ended, the same interrupt occurs again? Will the active ISR run to its end or will it be interrupted?

 

4)

Is there any possibility that an ISR is not executed until its end? The activate_HISR()-routine does some OS-specific stuff. fetching pointers, some if/else, lockout all interrupts for putting a pointer on a list and permitting all interrupts again. (for those, who know: OS is Nucleus, activate_HISR() calls NU_Activate_HISR().)

 

Sometimes I am missing the results of the activate_HISR()-routine. It seems, that it was not executed. So I modified the ISR for some testing.

 

original ISR:

interrupt void TpuInterruptEntry12(void)

{

   ClearIntRequest();

   activate_HISR();

}

 

modified ISR:

int TCRSTATE = 0;

interrupt void TpuInterruptEntry12(void)

{

  if (TCRSTATE != 0)

  {

       TCRSTATE++;

       ClearIntRequest();

       TCRSTATE = 0;

  }

  else

  {

       TCRSTATE = 1;

       ClearIntRequest();

       activate_HISR();

       TCRSTATE = 0;

  }

}

 

Sometimes the ISR runs into the if-case. I thought this could not happen.

There are other interrupts which use the same ISR but run without any problems.

 

 

 

Thanks.

 

vy 73

Dirk

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